FPGA Design Engineer

Arista Networks•Roseville, CA

4h•$110,000 - $170,000•Onsite

About The Position

Arista Networks is seeking an FPGA Design Engineer to join their Hardware Design Engineering team. This role involves developing high-speed networking and Ethernet products for enterprise campuses, hyperscaler data centers, and AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions. As a core member of the FPGA Design and Verification team, you will drive the development of high-performance control path FPGAs powering Arista’s flagship data center platforms. You will own the full design lifecycle—from gathering architectural requirements and reviewing board schematics to executing rigorous verification, leading system bring-up, and supporting production deployment.

Requirements

5 years or more of hands-on experience in Verilog/SystemVerilog RTL design.
Proven background in Control Path design.
Direct experience with On-Chip Bus interfaces (e.g., I2C, SPI, MDIO, PCIe, AXI).
Local to the Bay area

Nice To Haves

Experience with Ethernet Data Path architecture and design.
Hands-on experience with Streaming Bus interfaces (e.g., AXI-Stream).
Background in FPGA resource management and timing closure.
Proficiency in Python, Tcl, or general scripting for EDA tool automation.
Lab Debugging & Validation: Utilize logic analyzers (LA), oscilloscopes, and vendor-specific debug tools for lab bring up, debug, and validation.

Responsibilities

Develop, integrate, simulate, and verify Verilog and SystemVerilog RTL code, including custom testbench creation.
Execute the full FPGA development flow, including synthesis, place and route, timing closure, and in-system hardware debugging.
Collaborate directly with hardware and software engineering teams to drive rapid bring-up and debugging of next-generation network switch platforms.
Actively participate in peer RTL code reviews, as well as PCB schematic and board design reviews.
Develop AI-skills, Python, Tcl, or shell scripts to streamline data processing and automate FPGA design workflows.