Sr Foundry Engineer

BLUE ORIGINSpokane, WA
Onsite

About The Position

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight! We are seeking a Senior Foundry Engineer to serve as the primary technical interface with world-class semiconductor foundry partners (e.g., TSMC, GlobalFoundries, STMicroelectronics) and to own all aspects of process enablement, PDK readiness, tapeout execution, and process quality monitoring. This role is critical to ensuring our RFIC/ASIC design teams have reliable, qualified process technologies and toolsets to develop cutting-edge integrated circuits that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.

Requirements

  • MS or PhD in Electrical Engineering, Materials Science, or a related technical discipline.
  • 10+ years of experience in foundry engineering, process integration, or semiconductor technology enablement roles, with direct experience interfacing with major foundries.
  • Deep working knowledge of PDK architecture and qualification across advanced CMOS, SiGe BiCMOS, and/or RF SOI process technologies.
  • Extensive hands-on experience managing tapeout flows end-to-end, including physical verification signoff (DRC, LVS, antenna, DFM), GDS streaming, and foundry submission protocols.
  • Strong understanding of semiconductor device physics, process parameters, SPICE modeling (BSIM, HiCUM, PSP), and statistical process control (SPC/Cpk) methodologies.
  • Proficiency with EDA toolsets and associated verification and extraction tools.

Nice To Haves

  • Demonstrated ability to analyze WAT/e-test data, process control monitor (PCM) results, and lot-to-lot variability to assess process health and drive yield improvements.
  • Knowledge of advanced packaging technologies (flip-chip, fan-out wafer-level packaging, 2.5D/3D integration) and their foundry enablement requirements.
  • Experience with RF/mmWave process technologies (e.g., SiGe BiCMOS, RF SOI, GaN, InP) and associated device characterization.
  • Proficiency in scripting and automation (Python, Perl, TCL, SKILL) for PDK validation, data analysis, and tapeout flow automation.
  • Experience with space-grade, automotive-grade, or high-reliability qualification flows (e.g., QML, AEC-Q100, JEDEC standards).

Responsibilities

  • Serve as the primary technical liaison with external foundry partners, managing day-to-day communications, issue resolution, technology access agreements, and roadmap alignment.
  • Own PDK (Process Design Kit) availability, including version control, validation, and deployment across internal design teams; coordinate PDK updates, patches, and custom rule deck modifications with foundry and EDA team.
  • Manage end-to-end tapeout submissions, including GDS preparation, DRC/LVS/DFM signoff coordination, reticle scheduling, wafer lot tracking, and delivery logistics to ensure on-time and error-free tapeouts.
  • Support process and device model qualification, including SPICE model correlation, corner/Monte Carlo validation, and tracking of model-to-silicon accuracy across technology nodes.
  • Collaborate with production engineering to establish and maintain process Cpk parameter tracking systems, monitoring critical parametric data (Vt, Idsat, resistor/capacitor tolerances, etc.) to identify trends, excursions, and yield-impacting variations; drive corrective actions with foundry partners as needed.
  • Evaluate and recommend new process technologies and nodes based on design team requirements, performance targets, cost, and long-term roadmap fit for space-grade applications.
  • Develop and maintain internal documentation, dashboards, and reporting for tapeout schedules, foundry lot status, wafer acceptance test (WAT) results, and process health metrics.
  • Support production engineering wafer acceptance testing (WAT) and reliability qualification activities, including HTOL, ESD, and latch-up evaluations in coordination with foundry and internal quality teams.

Benefits

  • Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
  • Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
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