Sr Design Engineer

Micron Technology • San Jose, CA

1d • $93,000 - $198,000

About The Position

As a Sr. Design Engineer in the NVE Design Engineering Core group at Micron Technology, Inc., you will contribute to the development of memory products that are best-in-class, using your specialized knowledge and Micron proprietary methods of designing and analyzing core and mixed circuits used in the development of memory products.

Requirements

• MS/PhD preferred, BS in electrical engineering or equivalent experience required. 2+ years of NAND design relevant industry experience required.
• A high level of self-motivation.
• Good fundamentals in semiconductor and device physics and analog/mixed-signal circuit design. An understanding of semiconductor reliability issues including CHC, NBTI, stress, and snapback, as well as Electromigration (EM) and IR analysis.
• Strong circuit debugging and problem-solving skills.
• Experience in circuit verification and optimization, layout planning, parasitic extractions related to the circuits, experience guiding layout.
• Strong coding skills in Python (plus Bash/Tcl a bonus), and comfort working with structured data (CSV/JSON/SQLite) and version control.
• Excellent teamwork attitude. Good verbal communication skills (English) and ability to convey complex technical concepts in verbal and written form.

Nice To Haves

• Knowledge of analog and digital simulators such as HSPICE, Fast SPICE, and Verilog
• Familiarity with Cadence design, LVS/DRC tools (a plus).
• Experience with a scripting language.
• Familiarity with Linux/UNIX

Responsibilities

• Develop array waveforms with detailed timing and biasing conditions of array signals. This requires in-depth familiarity of Nand Flash memory read, program and erase algorithms.
• Collaborate with Firmware team, Analog team and Design validation teams during actual implementation of waveforms.
• Plan the wordline and bitline path architecture according to area, performance and power specifications. Establish the positioning of these electronic units and coordinate with project groups to embed these circuit blocks into the chip plan.
• Perform die size cost and benefits analysis of new array circuits and algorithms prior to implementation. Working closely with other functional teams to evaluate, analyze, and improve NAND power consumptions.
• Generate Xpath, Ypath and Array schematics as the project progresses and work with project teams integrating the Core schematics into the fullchip schematics. Run block level simulations for the circuits using spice simulator and coordinate layout implementation related to the circuits. Run subsystem and fullchip simulations throughout the course of the project.
• Develop and support Python AI utilities that integrate with EDA environments to accelerate tasks. These tasks cover environment setup, corner execution, regression runs, automated documentation, and smart design or layout methods.
• Review existing and generate new user documentation.
• Working with and supporting the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products to optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction.

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior