Sr. ASIC Verification Engineer (TERADYNE, North Reading, MA)

Teradyne•North Reading, MA

6d•$154,900 - $307,600•Onsite

About The Position

As a Sr. ASIC Verification Engineer based in North Reading, MA, you will play a key role in the development and verification of complex ASIC and SoC designs that support Teradyne’s industry-leading products. You will join the ASIC Reference Model team so this requires strong technical expertise in digital design verification methodologies, collaboration across engineering disciplines, and the ability to contribute to strategic verification initiatives while driving quality and execution excellence. This senior role aligns with professionals who work on complex issues requiring conceptual thinking, implement solutions for broadly defined problems, and contribute to the success of larger cross-functional projects.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field; Master's degree preferred.
8+ years of ASIC/SoC verification experience in semiconductor product development.
Strong experience with SystemC and C++.
Strong Object Oriented Programming experience.
Strong experience developing verification environments using SystemVerilog and UVM.
Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.
Experience with assertion-based verification and scripting using Python, Perl, or similar languages.
Knowledge of industry-standard EDA simulation and debug tools.
Experience verifying complex digital designs, interconnects, memory subsystems, and high-speed interfaces.
Strong analytical and problem-solving skills with the ability to debug complex functional issues.
Excellent collaboration and communication skills in a cross-functional engineering environment.

Nice To Haves

Preferred experience with formal verification methodologies.
Preferred experience supporting silicon bring-up and post-silicon validation activities.

Responsibilities

Lead verification planning, testbench architecture, and execution for complex ASIC and SoC designs.
Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage.
Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies.
Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities.
Partner with cross-functional teams to define verification requirements, milestones, and quality metrics.
Mentor junior engineers on verification methodologies, coding practices, and debugging techniques.
Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives.