LTD RET Software/Research Engineer

Intel•Hillsboro, OR

11d•$149,600 - $284,580•Hybrid

About The Position

This position is part of Intel’s Logic Technology Development (LTD) team, specifically the Resolution Enhancement Technology (RET) team. The team extends the feature sizes that can be patterned on Intel devices using current and future lithography manufacturing tools. It works with fab integrated lithography process and mask manufacturing teams to use computational lithography tools to optimize mask patterns and improve manufacturing process capability. The team also partners with design rule definition teams, using lithography and patterning simulation to determine design rules for future process nodes. The engineer develops and implements Optical Proximity Correction (OPC) algorithms and other Resolution Enhancement Techniques for existing and novel process technologies. The role applies predictive modeling, statistics, machine learning, and other data-analysis methods to fab process data, and develops software to compensate for physical effects in photolithography imaging and etch pattern transfer. It also supports production mask tapeout and RET validation, maintains knowledge of RET and semiconductor technology trends, and creates technical documentation and presentations. The role is hybrid, allowing employees to split time between the assigned Intel site and off-site work. The primary location is Hillsboro, Oregon. The position is an experienced hire on Shift 1. The stated U.S. annual salary range is $149,600–$284,580, with individual pay depending on location and additional factors.

Requirements

Bachelor’s degree in a relevant field and 6 or more years of professional experience in the semiconductor industry, or a master’s degree in a relevant field and 4 or more years, or a Ph.D. in a relevant field and 2 or more years.
Relevant fields include Computer Science, Software Engineering, and Electrical Engineering.
Hands-on professional experience in one or more of the following: pattern synthesis and mask layout manipulation; knowledge of OPC concepts and capabilities.

Nice To Haves

Understanding of the latest techniques for developing and optimizing OPC rule-based synthesis solutions to support both high-volume and newly developing technology nodes.

Responsibilities

Develop and implement Optical Proximity Correction (OPC) algorithms and Resolution Enhancement Techniques (RET) for existing and novel process technologies.
Define and select new approaches and implement RET.
Optimize and validate OPC recipe code.
Perform algorithmic design pattern layout manipulation.
Use predictive modeling, statistics, machine learning, and other data-analysis techniques to collect, explore, and visualize fab process data and develop RET software algorithms and applications to compensate for physical effects in photolithography imaging and etch pattern transfer.
Support production mask tapeout and RET validation.
Maintain a deep knowledge of state-of-the-art principles and trends in RET and semiconductor technology.
Create technical documentation and presentations.