The Receiver, Exciter, and Processing Architecture Department designs, architects, and implements signal-processing algorithms for next-generation radar systems. The team works across high-performance processing platforms, including CPUs, FPGAs, and GPUs, using commercial off-the-shelf and semi-custom hardware. The intern will contribute to system integration for distributed, heterogeneous signal-processing systems running Linux; develop, test, and integrate embedded or real-time C++ signal-processing algorithms and control functions; resolve defects and maintain existing code; analyze numerical accuracy, runtime latency, and other system metrics; collaborate with systems, hardware, and software engineers to implement end-user requirements; and help maintain code quality through reviews, static analysis, and continuous integration. The position is onsite in Marlborough, Massachusetts. U.S. citizenship and the ability to obtain and maintain a U.S. government security clearance are required; an active and existing DoD Secret clearance is required after day one.
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Job Type
Full-time
Career Level
Intern