Software Engineer - FPGA-Accelerated RTL Simulation
About The Position
The Role You will be responsible for the C++ application that constitutes the software-component of our custom hardware emulation framework (originally based on FireSim, https://fires.im). Join a small team (<5 engineers) working on a cross-cutting project that spans the whole stack. You will work closely with: FPGA RTL Designers: Components of our FPGA-hosted emulators are written in Chisel and optimized for Xilinx FPGAs. Compiler Developers: We compile ASIC RTL down to deterministic, FPGA-friendly emulation RTL using a purpose-built compiler based on MLIR & CIRCT. RISC-V Software & HW Developers: Build debug tools to help users co-design and debug novel RISC-V hardware and software. Your experience should be rooted in high-performance, multithreaded C++ application development. Familiarity with compiler development (ideally LLVM or MLIR) or FPGA RTL design is highly desired, but not required. You will help build the next generation of hardware emulation capacity for our RISC-V core IP—making it fast for software development, productive to debug, and cost-effective for deployment to every engineer in the company.
Requirements
- BS/MS/PhD in CS, CE, or EE.
- 7+ years experience building complete C++ applications, using modern C++ language features and best practices (C++20 and newer).
- Strong understanding of C++ concurrency features and demonstrated experience building multithreaded applications.
- Self-directed, with strong oral and written communication skills.
Nice To Haves
- Familiarity with compiler development (ideally LLVM or MLIR) or FPGA RTL design is highly desired, but not required.
Responsibilities
- Responsible for the C++ application that constitutes the software-component of our custom hardware emulation framework.
- Work closely with FPGA RTL Designers, Compiler Developers, and RISC-V Software & HW Developers.
- Build debug tools to help users co-design and debug novel RISC-V hardware and software.
- Help build the next generation of hardware emulation capacity for our RISC-V core IP.
Benefits
- Comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
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What This Job Offers
Job Type
Full-time
Career Level
Senior
