SoC Verification Lead

NVIDIA•Us, CA

11h

About The Position

NVIDIA is seeking an outstanding SoC Verification Engineer to serve as a Person-in-Charge (PIC) within the SoC Verification (SoCV) team. You will play a central role in verifying the most sophisticated AI-enabled SoC designs in the world. These chips power data center AI infrastructure, AI client computing platforms, autonomous vehicles, and robotics. This is a high-impact role combining deep technical expertise and multi-functional project leadership. It is ideal for someone who thrives on driving clarity in complex, fast-paced environments.

Requirements

Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
15+ years of hands-on experience in ASIC/SoC functional verification.
Deep understanding of SoC-level verification challenges and flows — from block integration through full-chip simulation and tape-out sign-off.
Consistent track record to lead or coordinate verification efforts across multiple IPs, multi-functional teams, and across the globe.
Outstanding time management skills — able to prioritize effectively across parallel workstreams under schedule pressure.
Demonstrated experience with project risk identification, tracking, and mitigation.
Proficiency in SystemVerilog and UVM-based testbench development; familiarity with C/C++ for directed and hardware-controlled test development at the SoC level.
Solid grasp of verification infrastructure: EDA tool configuration, regression automation, job farm management, and environment maintenance.

Nice To Haves

Experience owning or contributing to verification sign-off at SoC tape-out achievements.
Prior track record as a verification PIC or tech lead across a full SoC project lifecycle, from spec to silicon bring-up.
Familiarity with coverage closure methodologies — functional, code, and assertion-based.

Responsibilities

Own the SoC-level verification plan, schedule, and achievement tracking from the conception of project through tape-out, serving as the primary PIC across all verification workstreams.
Collaborate with architects, IP owners, emulation team, FPGA team, and infrastructure engineers to align on coverage goals, resolve bottlenecks, and ensure verification requirements are met at every project stage.
Drive verification status reviews, track open issues across teams, and proactively bring up risks to project leadership with clear mitigation plans.
Lead risk identification and mitigation planning throughout the verification lifecycle, maintaining clear communication with collaborators.
Partner with tape-out teams to define and close verification sign-off criteria at each tape-out achievement.
Define and continuously evolve SoC verification flows and methodologies to meet the demands of next-generation AI-enabled chip complexity.