Senior Staff SOC Verification Engineer
About The Position
Silicon Labs is seeking a Senior Staff Digital Verification Engineer for their Wireless MCU products team in Austin, TX. This team is responsible for the architecture specifications, design, verification, emulation, and implementation of Wireless MCU SoCs. The IPs include an embedded CPU system with analog and digital peripherals, advanced security, advanced power management, and best-in-class low-power wireless modems. The team also focuses on innovation in custom RISC-V Cores and AI/ML accelerators. The role involves executing a verification plan on digital IP blocks using simulation and formal verification techniques, building UVM test benches from scratch, and interacting with cross-functional teams to debug IP and system-level issues. The engineer will also debug chip-level tests for functionality, power, and performance as needed.
Requirements
- 10+ years of design verification experience
- Bachelor's or Master's degree in Electrical/Computer Engineering
- Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++
- Knowledge of digital design, ARM, or RISC-V architecture and bus protocols
- Knowledge of CPU subsystem and memory controller verification
- Knowledge of scripting languages like Perl, Python, Tcl, and shell
- Experience in architecting complex verification environments from scratch
- Advanced verification skill in SVAs, constrained random stimulus, and coverage analysis
- C-based testcase development and debugging skills
- Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making
Nice To Haves
- Familiarity with Flash/RRAM Controller architecture
- Verification and debug of low-power design with UPF
- Technical leadership and mentoring experience
- Good written and oral communication skills
Responsibilities
- Block and IP Verification
- Create and execute the test plan with emphasis on metrics driven verification
- Constrained random tests, scoreboard, and coverage development
- Validate block power and performance requirements
- Apply formal verification tools like lint, auto, and property checks
- System Level Verification
- Debug functional failures at subsystem and SoC levels
- Perform gate-level verification across corners and provide activity files for power analysis
- Flows and Methodology
- Architect and implement Verification Components using UVM-based methods
- Develop verification flows and methodologies to enhance IP, SoC, and Formal Verification
Benefits
- Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans
- Highly competitive salary
- 401k plan with match and Roth plan option
- Equity rewards (RSUs)
- Life/AD&D and disability coverage
- Flexible spending accounts
- Adoption assistance
- Back-Up childcare
- Commuter benefits
- Legal benefits
- Pet insurance
- Flexible PTO schedule
- 3 paid volunteer days per year
- Charitable contribution match
- Tuition reimbursement
- Free downtown parking
- Onsite gym
- Monthly wellness offerings
- Free snacks
- Monthly company updates with our CEO
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What This Job Offers
Job Type
Full-time
Career Level
Senior
