SoC Verification Engineer – NoC / UVM

Advanced Micro Devices, Inc•San Jose, CA

4h•Hybrid

About The Position

The verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.

Requirements

Skilled verification engineer with strong expertise in SystemVerilog and UVM
Solid understanding of ASIC/SoC verification methodologies
Experience verifying complex digital designs, ideally including NoC architectures
Proficient in constraint-random, coverage-driven, and formal verification (SVA)
Analytical, detail-oriented, and collaborative
Ability to debug complex issues
Drive verification closure
Effectively partner with global design and architecture teams while taking ownership of challenging problems

Nice To Haves

Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
Strong understanding of different phases of ASIC and/or full custom chip development is required.
Experience in block level NOC (Net work on Chip) verification is a plus.
Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.
Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.

Responsibilities

Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
Interact with architects and design engineers to create a comprehensive verification testplan
Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks
Identify and write coverage measures for stimulus quality improvements
Perform coverage analysis to identify verification holes and achieve closure on coverage metrics