Senior Hardware Design Verification Engineer (SystemVerilog/UVM)

Team Red Dog•Redmond, WA

4d•Remote

About The Position

Team Red Dog is hiring a Senior Hardware Design Verification Engineer (SystemVerilog/UVM) for our client, a leading cloud and software provider and industry-leading technology partner. In this fully remote role, you'll help verify the next generation of Azure networking hardware, contributing to Azure Boost SmartNIC and FPGA technologies that power one of the world's largest cloud platforms. You'll develop and execute SystemVerilog/UVM verification solutions, create comprehensive test plans, automate verification workflows, and partner closely with hardware design engineers to ensure high-quality, high-performance silicon. This is a rare opportunity to influence cutting-edge cloud infrastructure while working on technologies deployed at hyperscale.

Requirements

SystemVerilog & UVM (7+ years preferred) – Develop, enhance, and execute verification environments, testbenches, assertions, sequences, constraints, and functional coverage for complex IP and SoC hardware designs.
Hardware Design Verification – Perform pre-silicon verification, execute comprehensive test plans, drive coverage closure, debug design issues, and collaborate closely with RTL design teams throughout the development lifecycle.
Networking Hardware & Industry Protocols – Experience verifying networking or storage datapaths with knowledge of protocols such as Ethernet, PCIe, AXI, and AHB within complex hardware systems.
Python and/or Perl Automation – Develop scripts that automate regression testing, continuous integration (CI), verification workflows, and test execution to improve engineering efficiency.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Approximately 7+ years of hands-on hardware design verification experience using SystemVerilog and UVM.
Strong experience performing IP and/or SoC-level pre-silicon verification.
Solid understanding of RTL design concepts and modern verification methodologies.
Knowledge of networking protocols including Ethernet, PCIe, AXI, AHB, or similar high-speed interfaces.
Experience developing automation using Python and/or Perl.
Strong debugging, analytical, and problem-solving skills.
Ability to work independently within established verification environments.
Excellent communication and collaboration skills.
Ability to support Pacific Time working hours with approximately 2–3 hours of overlap.
Ability to commit to an engagement expected to last approximately 18 months.
All applicants must be authorized to work in the U.S. without the need for sponsorship.

Nice To Haves

Experience verifying networking or storage hardware preferred.
Deep expertise in SystemVerilog, UVM, and hardware design verification.
Ability to quickly contribute within an existing verification environment.
Experience validating complex IP or SoC designs, developing reusable verification components, driving comprehensive coverage closure, and collaborating effectively with hardware design teams to resolve challenging issues.
Experience verifying networking hardware, SmartNICs, storage datapaths, FPGA technologies, or cloud infrastructure components is highly valued.
Proven ability to independently own verification efforts from planning through execution and debugging.

Responsibilities

Develop comprehensive verification plans for new hardware features and functionality.
Execute verification strategies using SystemVerilog and UVM within established verification environments.
Create and enhance sequences, assertions, constraints, scoreboards, and functional coverage.
Design directed, constrained-random, and stress test scenarios to validate functionality and corner cases.
Drive functional, code, assertion, and test plan coverage to verification closure.
Debug complex hardware issues and partner with RTL designers to resolve functional and performance defects.
Develop Python and/or Perl automation scripts supporting regression testing and CI/CD workflows.
Participate in Agile development activities including sprint planning, code reviews, and iterative feature development.
Analyze regression results, perform root-cause analysis, and support bug triage activities.
Improve verification quality through error injection, congestion, recovery, and backpressure testing.