SoC Top-Level Physical Design Engineer
About The Position
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level SoC Physical Design Engineer to drive top-level implementation of our complex AI and CPU SoC designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Ft. Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules
Requirements
- 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
- Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
- Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
- Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Industry
Professional, Scientific, and Technical Services
Education Level
No Education Listed
Number of Employees
501-1,000 employees
