SoC Silicon Top-Level Floorplan Engineer

Google • Sunnyvale, CA

1d

About The Position

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be creating the initial physical layout of a chip top-level, defining block sizing/placement, power grids, and clock distribution to meet performance, power, and area (PPA) goals, requiring deep collaboration with architecture, RTL, and synthesis teams, using industry and internal tools, and driving early timing/congestion closure for complex modern SoCs. You will utilize full-chip planning and IP integration, delivering floorplan collaterals and collaborating for signoff. This is a highly cross-functional and central role that will require interactions with numerous development teams. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in physical design (e.g., with a focus on floorplanning, integration, or top-level chip assembly).
• Experience in physical design working on advanced nodes.
• Experience collaborating with cross-functional teams (e.g., architecture, RTL design, synthesis, verification).
• 3D IC design experience (e.g., multi-die partitioning, TSV planning, advanced chiplet and packaging technologies, optimizing PPA, and physical verification in a System-in-Package context).

Nice To Haves

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in scripting languages (e.g., Python, Tcl or Perl) and industry standard top-level tools including Innovus, FusionCompiler.
• Experience working on various technologies (e.g., embedded processors, DDR,SerDes, HBM, networking-on-chip fabrics, etc.).
• Experience using specialized EDA tools to resolve DRC/LVS/EMIR issues for leading edge nodes.
• Experience with SoC design methodologies for full chip power grid, global clocking, data path implementation, 3PIP integration, and bump planning.

Responsibilities

• Own the planning, creation, and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume.
• Resolve structural or physical issues related to the integration of complex ASICs and SoCs and collaborate with teams across Google to develop ideas for high impact Silicon and Hardware projects.
• Manage all cross-functional interactions related to top-level floorplanning of chip projects.
• Develop and improve floorplan implementation methodologies.
• Support and execute implementation flows using both industry-standard and specialized internal tools.
• Perform technical evaluations of vendors and IP, providing recommendations and assessment of process node tradeoffs to meet performance, power, area and cost goals.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees