SoC QoS/Fabric Performance Engineer, Platform Architecture

Apple•Cupertino, CA

About The Position

The SoC QoS/Fabric Performance Engineer will join Apple’s Platform Architecture team and work with hardware and software engineering groups to shape the architecture of future Apple System-on-Chips (SoCs). The role focuses on developing on-chip communication interconnect and memory Quality-of-Service features and creating a full-chip C++ simulator for iPhone, iPad, Mac, and Watch SoCs. The engineer will model emerging workloads, including Augmented Reality (AR) and Machine Learning (ML), and use those models to study performance and power trade-offs. The work supports architecture improvements for future Apple products and includes learning about state-of-the-art SoC IP and chip-level architecture, building network-on-chip models, running performance simulations, analyzing results, and tuning and validating future SoC hardware and software for the best user experience. The position involves collaboration with cross-functional modeling, hardware, and software teams. Some international travel is required.

Requirements

Bachelor of Science degree.
C++ programming experience.
Coursework and/or experience in computer architecture and the hardware/software stack.
Coursework and/or experience with performance modeling and debugging.
Examples of substantial hardware or software projects brought to completion.
Coursework and/or practical experience with scripting for automation and data visualization.
Coursework and/or practical experience with network-on-chip architecture and design.
Ability to study a problem in depth, design experiments, analyze data, and present results.
Experience with Cellular/5G modem architecture.
Communication and documentation skills.

Responsibilities

Develop on-chip communication interconnect and memory Quality-of-Service features.
Help create a full-chip C++ simulator for iPhone, iPad, Mac, and Watch SoCs.
Model emerging workloads such as Augmented Reality (AR) and Machine Learning (ML).
Study SoC performance and power trade-offs using workload models.
Learn and work with SoC IP and chip-level architecture, including network-on-chip C++ modeling of graphics, camera, and ML dataflow and integration with other SoC models.
Run performance simulations of future applications.
Analyze and present simulation results carefully.
Tune and validate future SoC hardware and software for the best user experience.
Collaborate with cross-functional modeling, hardware, and software teams.
Travel internationally as required.