SoC Performance Architect

Qualcomm•Santa Clara, CA

1d•$167,000 - $250,600

About The Position

As a SoC Performance Architect, you will create performance and power models for the fabric NoC / DRAM controller / IO blocks for server-class SoCs, correlate models against RTL behavior, prototype ideas and help productize performance/power features for future SoC designs.

Requirements

2+ years of experience in SoC performance/power modeling
Strong grasp of the computer architecture fundamentals especially in the areas of interconnects, traffic QoS, distributed caches, coherency flows, DRAM controller and IO (PCIe) flows
Proficient in C++ and Perl / Python
Exposure to performance analysis and debug
Ability to independently identify, troubleshoot and solve performance problems
Bachelor's degree in Electrical Engineering, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
Master's degree in Electrical Engineering, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.
PhD in Electrical Engineering, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.
2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).

Nice To Haves

4 years of experience in CPU / SoC performance/power modeling, Performance Validation
Proficient in IP/SoC level performance validation between RTL and performance models,
Expertise in analyzing and debugging performance shortfalls in RTL environment
Exposure to testing and debugging performance issues post-silicon environments
Demonstrable experience in productizing features that improve performance/power characteristics of a design

Responsibilities

Conduct RTL performance verification. This will involve creation of verification plans and directed tests / checkers
Develop a SoC performance/power model for blocks such as interconnect NoCs, distributed system caches, memory controllers, IO controllers
Verify model correctness by writing unit-tests and debugging mismatches against expectations
Identify ideas for improving the SoC’s performance/power characteristics. Prototype idea in the performance/power model and thoroughly characterize it
Work with architects and RTL developers to productize the improvements identified through detailed studies