SoC Logic Design Engineer

Intel•Us, MA

2d•Hybrid

About The Position

In this role, you will be part of the SoC Logic Design Engineering team, contributing to the design and integration of next-generation Xeon server product SoCs and IPs. You will develop RTL designs, integrate IP blocks, and perform quality checks to ensure performance, power, and timing goals are achieved. Your work will play a critical role in shaping future server technologies, enabling innovative solutions for Intel's global clients. Business groupAs a member of Intel's Xeon Engineering Group (XEG), you will join a team dedicated to developing advanced server product SoCs and IPs. The group focuses on delivering high-performance, secure, and scalable solutions that support Intel's broader mission to create world-changing technology. Working within this dynamic and collaborative environment, you will have the opportunity to contribute to impactful projects that drive innovation in enterprise computing.

Requirements

Bachelor's Degree in Electrical Engineering, Computer Engineering, or Computer Science with 0-1 years of hands-on experience in SoC logic design, integration, and validation, with demonstrated skills gained through internships, academic projects, coursework, or hands-on training, OR a Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science with no prior professional experience.
Proficiency in System Verilog for RTL design and logic development.
Experience with Synopsys tools such as VCS/Modelsim, Design Compiler, Spyglass, or Lint.
Familiarity with scripting languages like Perl, Tcl, Python, or C++.

Nice To Haves

Courses or academic projects related to IC/SoC design and integration.
Knowledge of low-power design techniques and clock domain crossing.
Strong problem-solving and collaborative skills, with the ability to work across diverse teams.
Enthusiasm for innovation and a passion for advancing server technologies.

Responsibilities

Develop and optimize RTL designs for SoC components using System Verilog.
Integrate IP blocks and subsystems into full-chip SoCs, ensuring architectural accuracy and smooth handoffs.
Conduct quality checks on RTL designs to meet timing, power, performance, and area goals.
Resolve RTL test failures by implementing corrective measures and ensuring design feature correctness.
Collaborate with validation teams to identify and address bugs, implementing solutions for both SoC RTL and tiles.
Work closely with physical design and architecture teams to ensure alignment with design and implementation objectives.
Apply secure development practices to address security threats within the design.
Utilize scripting and automation tools to improve design workflows and efficiency.