Principal PCIe Logic Design
About The Position
Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. This full-time position will allow the candidate to contribute to the architecture, design of next generation IPs, targeting the latest developments in PCIe standards. This position will also be involved in prototyping these IPs on cutting edge FPGAs. The candidate will work closely with local teams as well as with multi-cultural, multi-national colleagues. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Requirements
- RTL coding: Verilog / System Verilog
- Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent.
- 8+ years of experience with RTL Design
- Good English skills, communication skills, and willingness to work with an international team.
Nice To Haves
- Knowledge of PCIe / CXL
Responsibilities
- Contribute to the architecture and micro-architecture of next generation PCIe IP
- Implement these designs in System Verilog
- Collaborate with the verification team to verify the IPs
- Participate in prototyping of the IPs in cutting edge FPGAs
- Contribute to support of existing generations of the IPs
Benefits
- matching 401(k)
- employee stock purchase plan
- comprehensive medical and dental benefits
- time-off program
- gym membership
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What This Job Offers
Job Type
Full-time
Career Level
Principal
