SoC Interconnect and Fabric RTL Designer

TYLsemi•San Jose, CA

33d•Hybrid

About The Position

We are looking for a System On-chip/SoC Fabric micro-architect and designer for chiplet-based AI and High-Performance Compute silicon development.

Requirements

BS/MS in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of digital IC design, with at least 4 years owning on-chip interconnect, bus fabric, or NoC architecture at block-lead or integration-lead level.
Deep expertise in one or more on-chip interconnect protocols: AXI4 / AXI4-Lite / AXI-Stream; CHI or equivalent; able to write and review bus bridge RTL and understand ordering rules, response channels, and error signaling.
Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC).
Familiarity with AMBA CHI or ACE coherency extensions and their impact on fabric design.
Solid understanding of CDC design: async FIFO design, gray-code counters, synchronizer topologies, and CDC verification methodology.
Experience owning the top-level integration netlist or chip-level assembly RTL on a multi-block design.
Strong SystemVerilog skills: arbiters, FIFOs, pipelines, address decoders, and parameterized bus infrastructure.
Experience with static timing constraints for multi-clock designs

Nice To Haves

Background with high-speed chiplet or SoC integration at advanced nodes (7 nm or below), including floorplan-driven bus topology decisions.
Experience building or maintaining an automated register-map generation flow (SystemRDL, IP-XACT, or similar).
Prior role as chip-level integration lead responsible for assembling subsystem IPs into a complete design.
Familiarity with hardware security primitives: access control, firewall IP, or trusted execution region isolation in the fabric.
Experience with formal property verification of bus protocols or CDC crossings.

Responsibilities

Define on-chip fabric topologies connecting the multiple subsystems
Specify the data-path fabric for the high-bandwidth routes: bandwidth provisioning, pipeline depth, buffering strategy, and back-pressure propagation between major subsystems.
Architect the register-access fabric with address decoding and access-protection logic.
Define the arbitration and QoS policy for shared fabric resources: priority assignment per traffic class, bandwidth reservation, and starvation-prevention mechanisms.
Own the fabric error-handling architecture: how illegal accesses, timeouts, and protocol violations are detected, logged, and reported to the management subsystem.
Own the CDC strategy for every clock-domain boundary on the die — and documenting the timing constraints for each.
Own or closely review all fabric RTL: bus bridges, async FIFOs, arbiters, address decoders, and pipeline registers that form the on-chip interconnect.
Drive integration assembly: own the top-level connectivity netlist that instantiates all major blocks and wires them through the fabric, serving as the integration point of truth.
Coordinate with subsystem leads align on interface protocols, handshake semantics, and reset sequencing at each fabric boundary.
Define and own the fabric performance model: estimate bandwidth utilization per path under representative traffic mixes for each operating mode and identify bottlenecks.
Establish fabric-level bring-up tests: register accessibility checks, path connectivity tests, and loopback sequences that confirm the interconnect is healthy before full subsystem integration testing begins.
Coordinate with the physical design team on fabric floorplan implications: block placement driven by dominant data flow, clock-region boundaries, and wire-length budgets for timing closure.