SoC Design Lead

TYLsemi•San Jose, CA

About The Position

We are seeking a highly skilled and collaborative SoC Front-End Lead to spearhead the technical direction, micro-architecture, and logic design of our next-generation semiconductor products. In this role, you will bridge the gap between high-level architectural requirements and physical reality, managing the front-end execution from micro-architecture to netlist delivery. You will lead a talented team of hardware design engineers and partner with cross-functional teams including Emulation and Firmware to deliver high-performance, low-power silicon.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
12+ years of digital design and RTL development experience, with a proven track record of delivering complex, production-grade SoCs.
Expert proficiency in SystemVerilog or Verilog for high-performance design.
Hands-on experience with industry-standard front-end tools (e.g., Synopsys SpyGlass, VC Formal, Cadence JasperGold) for Lint, CDC, and formal checks.
Deep understanding of digital design fundamentals, clock/reset structure design, and power intent specification (UPF/CPF).
Exceptional cross-functional communication skills to coordinate between architecture, physical design, firmware, and software teams.

Nice To Haves

Experience with high-speed protocols or fabric interconnects (e.g., PCIe Gen6+, CXL, CHI, or UCIe chiplet interfaces).
Familiarity with advanced semiconductor process nodes (e.g., 5nm, 3nm, or below).
Proficiency in scripting languages (Python, Perl, or Tcl) to automate design flows

Responsibilities

Lead, mentor, and scale the front-end design team. Set design methodology, coding standards, code-review processes, and execution timelines.
Translate product requirements into detailed micro-architectural specifications. Own block partitioning, data flow, and interface standards across the chip front-end.
Oversee the integration of internal and third-party IP blocks (e.g., PCIe, UCIe, CXL etc). Manage the integration of core pervasive logic including clocking, resets, pad rings, and power management (UPF).
Evaluate, pilot, and deploy AI-powered design assistants and LLM copilots within the RTL generation, code review, and documentation workflows to accelerate design velocity.
Ensure quality and signoff readiness across the front-end using static verification tools (Linting, Clock Domain Crossing/CDC, Reset Domain Crossing/RDC, and Logical Equivalence Checking/LEC).
Partner closely with physical design (back-end) teams to address timing constraints, area optimization, and floorplanning awareness early in the design cycle.
Work alongside Design Verification (DV) teams to define testing plans and coverage strategies. Collaborate with Design for Test (DFT) leads to inject scan-friendly structures and debug hooks into the RTL.
Act as a key technical contact during post-silicon laboratory bring-up, debugging, and issue triage.