SoC Design Engineer

OMNIVISION•Santa Clara, CA

1d•$156,853 - $160,000

About The Position

The SoC Design Engineer will be responsible for designing and verifying digital circuits for CMOS image sensors (CIS). This includes sensor array timing control logic, analog-digital interface modules, and ISP (Image Signal Processing) data pipelines. The role involves full-chip SoC integration, IP integration, clock/reset domain management, power-aware design, and system-level verification to ensure functional correctness and tape-out readiness. The engineer will also develop, integrate, and validate IPs through the complete ASIC design flow, conduct static timing analysis (STA), and collaborate with back-end physical design teams. Pre-silicon verification using UVM-based testbenches and scripting languages for automation will be a key part of the role. Additionally, the engineer will work with sensor analog/digital engineers on system-level architectures and mixed-signal functionality, partner with algorithm engineers on hardware-efficient microarchitectures and C/C++ reference models, and support post-silicon activities including chip bring-up and validation. Contributions to image tuning, sensor characterization, and product qualification are also expected, along with creating and maintaining technical documentation.

Requirements

Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a closely related field
One year experience in digital design.
Architecture for Wi-Fi 6 AP transmitter.
Wi-Fi PHY based RTL design and verification using Verilog.
Module-level verification and full-chip integration support.
Design optimization techniques for area, power, and timing.
Using industry-standard digital design and verification tools.

Responsibilities

Design and verify digital circuits for CMOS image sensors (CIS), including sensor array timing control logic, analog-digital interface modules, and ISP data pipelines.
Perform full-chip SoC integration, including IP integration, clock/reset domain management, power-aware design, and system-level verification.
Develop, integrate, and validate IPs through the complete ASIC design flow: RTL coding in Verilog/SystemVerilog, simulation, synthesis and DFT implementation.
Conduct static timing analysis (STA) for image sensor timing-critical paths.
Collaborate closely with the back-end physical design team on floor planning, timing closure, power optimization, and DFT strategy.
Perform pre-silicon verification using UVM-based testbenches, and scripting languages (Python, Perl) for automation, coverage analysis, and regression testing.
Work with sensor analog/digital engineers to co-develop system-level architectures, define interface protocols, and validate mixed-signal functionality.
Partner with algorithm engineers to implement hardware-efficient microarchitectures, develop C/C++ reference models, perform RTL-to-model co-simulation, and optimize hardware/software partitioning.
Support post-silicon activities including chip bring-up, silicon validation, debugging, and performance tuning.
Contribute to image tuning, sensor characterization, and product qualification by analyzing hardware behavior and providing feedback.
Create and maintain technical documentation, including architecture specifications, registers, interface control documents.