Senior SoC Design Verification Engineer

Intel Corporation•Santa Clara, CA

2d•$164,470 - $269,100•Hybrid

About The Position

As a Senior SoC Design Verification Engineer, you will lead verification efforts for complex system-on-chip (SoC) designs that enable Intel's next generation of client computing and AI technologies. You will drive verification strategy, architecture, methodology development, and execution across block, subsystem, and SoC-level verification environments. Working closely with architects, RTL designers, security engineers, and validation teams, you will help ensure industry-leading quality, functionality, security, and performance of Intel silicon products. In this highly visible role, you will influence verification methodologies, mentor engineers, and contribute to the continuous improvement of Intel's verification practices while helping deliver innovative products to market.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
8+ years of experience in SoC verification, including test planning, implementation, and debug.
System Verilog, OVM or UVM methodologies, and SoC test environment/VC development.
Debugging and root cause analysis in pre-silicon environments.
Experience with hardware simulation tools and methodologies.
System architecture, SoC architecture, and microarchitecture concepts.
Developing scalable, reusable, and maintainable verification environments.
Working closely with RTL designers and architects to verify complex digital designs

Nice To Haves

Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience with low-power design and verification techniques.
Python and scripting for automation of verification tasks.
Design for Test (DFT) tools and techniques.

Responsibilities

Perform functional logic verification of integrated SoCs to ensure designs meet specifications.
Define and develop scalable, reusable block, subsystem, and SoC verification plans, test benches, and verification environments.
Execute verification plans using emulation and system simulation models to analyze power, performance, and functionality.
Identify, replicate, root cause, and debug issues in the pre-silicon environment, implementing corrective measures to resolve failing tests.
Collaborate with SoC architects, microarchitects, RTL developers, post-silicon teams, and physical design teams to enhance verification methodologies.
Develop and execute security-focused test plans to ensure security coverage during regression and debug testing.
Maintain and improve existing functional verification infrastructure and methodologies for future products.
Incorporate learning from post-silicon validation to identify gaps and update test plans to improve coverage for subsequent projects.
Document test plans and conduct technical reviews with design and architecture teams.