SoC Data Path Engineer

Advanced Micro Devices, Inc•Markham, ON

2d•Hybrid

About The Position

We are seeking an experienced SoC Data Path Engineer to lead validation and debug of AMD's next-generation on-chip fabric and data transport architectures. This role focuses on post-silicon validation of fabric, coherency, memory, and compute data flows that enable communication across CPU, GPU, accelerator, and chiplet subsystems. You will play a critical role in ensuring performance, scalability, functionality, and reliability across complex multi-die products. As a SoC Data Path Engineer, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards product development, definition, and root cause resolution.

Requirements

Experience in post-silicon validation, hardware debug, or related semiconductor development roles, with demonstrated ownership of validation planning, execution, and milestone sign-off.
Strong understanding of SoC architecture, multi-die/chiplet systems, on-chip fabrics, coherency protocols, memory hierarchies, caches, DMA, interrupts, and address translation mechanisms.
Experience debugging complex silicon issues using scan dump analysis, JTAG-based tools, or similar debug methodologies, with the ability to root-cause system-level hangs, stalls, protocol violations, and performance bottlenecks.
Proficiency in C/C++, Python, Perl, or similar languages for validation automation, debug tooling, and workflow optimization.
Familiarity with graphics and compute architectures, GPU software stacks, runtime environments, and RAS features including error detection, fault handling, machine check logging, and system reliability mechanisms.
Bachelors or Masters degree in electrical or computer engineering

Responsibilities

Lead post-silicon validation and debug of SoC fabric, interconnect, and system-level data transport architectures across graphics and compute products.
Drive root-cause analysis of silicon issues involving coherency, routing, credit protocols, transaction ordering, memory interactions, and compute pipeline behavior.
Develop and execute comprehensive validation plans while improving coverage through automation, tooling, fault injection, and stress-testing methodologies.
Analyze scan dumps, silicon debug logs, and system telemetry to resolve hangs, stalls, synchronization failures, and protocol violations.
Collaborate with design, firmware, driver, runtime, and software teams to debug complex hardware-software interactions and deliver robust product solutions.
Lead cross-functional debug efforts spanning multiple IPs, chiplets, memory subsystems, and fabric domains to drive issue resolution and product readiness.