SoC Architect, Memory Subsystem

Samsung•San Jose, CA

1d•Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us! As a SoC Architect, you will play a key role in shaping the future of our premium chipsets by defining and driving the development of innovative SoC memory and cache subsystems. This is a technical contributor position that requires a foundation in architecture principles, as well as an understanding of memory subsystems, including memory hierarchies, interfaces, controllers, and caches. Your expertise will enable you to propose and implement new, efficient SoC memory architectures that meet the demands of our cutting-edge products.

Requirements

6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a PhD
Experience designing and developing complex digital systems and SoC memory architectures
Strong understanding of memory hierarchies, memory interfaces (e.g., DDR, LPDDR, HBM), and memory controllers is crucial
Detailed knowledge of cache subsystems including caching policies and understanding the tradeoffs of latency, bandwidth and hierarchies
Knowledge of memory scheduling, bandwidth management, and latency optimization
High familiarity with existing and emerging JEDEC memory standards
Strong written and verbal communication skills

Nice To Haves

Experience with cache coherence protocols and bus protocols (e.g., CHI, ACE, AXI) is a plus
Experience with the Android ecosystem and analysis tools is a plus
Experience with Arm architecture and ecosystem is a plus

Responsibilities

Identify, propose, and deliver new SoC memory architectures and features for premium mobile and related product platforms.
Contribute to high-impact deliverables, with the freedom to experiment and explore novel ideas to challenge existing norms and push the boundaries of what is possible.
Create detailed designs and specifications for memory subsystems, including memory interfaces, controllers, and caches.
Analyze PPA trade-offs and optimize memory subsystem performance, power consumption, and area utilization to meet system requirements.
Work closely with software, hardware, and validation teams to ensure memory subsystem designs meet system requirements and are properly integrated
Create and maintain detailed documentation of memory subsystem designs, including architecture, implementation, and verification plans.
Stay up-to-date with emerging memory technologies and recommend their adoption in SoC designs.