Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect

Samsung Research America•Mountain View, CA

4d•Onsite

About The Position

The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high-performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products. We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands-on role leading individual and team contributions to Fabric, System cache and DRAM controller sub-system architecture, interface, performance and power tradeoffs.

Requirements

BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
3+ years of experience in SOC or ASIC design and architecture
Prior direct experience (> 7 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required
Understanding of memory controller architecture, memory scheduling, prioritization and QoS
Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area

Nice To Haves

Experience with BookSim Simulator
Experience with Platform Architect

Responsibilities

Guide on development of innovative Fabric, System cache and DRAM controller Architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs
Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets
Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership)
Perform high-level performance modeling/simulation and analysis of Fabric, System cache and DRAM controller features, applications, benchmarks, and complex uses cases
Direct and orchestrate performance modeling, and studies to support inclusion of these features in the next generation “Fabric, System cache and DRAM controller” microarchitecture based on performance, area or power improvement
Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
Collaborate with silicon bring-up and product teams to verify and debug the proposal and its delivered performance
Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations