Silicon Validation Engineer
About The Position
MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.
Requirements
- Strong hands-on experience in silicon validation, post-silicon bring-up, hardware emulation, Top-level DV, or a related field.
- Experience validating complex SoCs, accelerators, or highly integrated silicon products.
- Strong understanding of digital hardware, SoC architecture, and hardware-firmware interaction.
- Proven ability to debug complex cross-functional failures and drive them to root cause.
- Experience working with real silicon and lab platforms.
- Familiarity with firmware, embedded software, drivers, and low-level hardware access.
- Ability to read and understand C or C++ code for debug purposes.
- Python or similar scripting experience.
- Ability to read specifications, register descriptions, validation plans, and relevant RTL.
- Strong ownership, communication, and cross-functional collaboration skills.
Nice To Haves
- Experience with both pre-silicon and post-silicon validation.
- Experience with Cadence Palladium.
- Experience with SystemVerilog, UVM, assertions, coverage, or waveform debug.
- Experience bringing up first silicon.
- Experience with HBM, DDR, PCIe, CXL, Ethernet, die-to-die interfaces, or advanced packaging.
- Familiarity with JTAG, oscilloscopes, logic analyzers, or protocol analyzers.
Responsibilities
- Own silicon bring-up and validation from first power-on through feature validation and production readiness.
- Develop and execute validation plans for chip-level and SiP-level functionality, performance, reliability, and system behavior.
- Validate boot, reset, initialization, power management, recovery, memory, interconnect, high-speed interfaces, and package-level functionality.
- Work across Top-level DV, Palladium emulation, lab validation, and package validation to improve coverage and correlation between environments.
- Debug complex failures using logs, registers, traces, waveforms, firmware output, and lab equipment.
- Analyze issues across RTL, firmware, software, board, package, and silicon boundaries.
- Collaborate with architecture, design, DV, emulation, firmware, software, and product engineering teams.
- Define observability and debug requirements and improve validation automation, execution, and failure triage.
Benefits
- Company subsidized Health, Dental, Vision, and Life insurance
- Pre-tax Health Savings Accounts with generous company contribution
- 4 weeks paid time off (accrued)
- 12 company holidays
- 3 weeks remote/flexible work per year
- Up to 12 weeks of paid parental leave
- $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
- Team Lunches, quarterly off-sites, and regular town halls
- 401K and/or Roth IRA, with 5% company contribution
- Flexible Spending Accounts
- Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
- $50 per month to use on the perks you care about most
- Remote Perks
- home-tech setup
- remote wifi expense reimbursement
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
Education Level
No Education Listed
