Silicon Validation Engineer

MatX • Mountain View, CA

3d • $120,000 - $475,000 • Hybrid

About The Position

MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• Strong hands-on experience in silicon validation, post-silicon bring-up, hardware emulation, Top-level DV, or a closely related field.
• Experience validating complex SoCs, accelerators, compute devices, or highly integrated silicon products.
• Strong understanding of digital hardware, SoC architecture, and hardware-firmware interactions.
• Proven ability to debug complex failures across hardware, firmware, software, package, and validation-environment boundaries.
• Experience working in a laboratory environment with real silicon and hardware platforms.
• Experience using logs, traces, register data, waveforms, and other debug information to isolate failures.
• Familiarity with firmware, embedded software, drivers, and low-level hardware access.
• Ability to read and understand C or C++ code as part of debug and failure analysis.
• Scripting and automation experience, preferably using Python.
• Ability to read hardware specifications, architecture documents, register descriptions, validation plans, and relevant RTL.
• Experience defining validation scenarios, test plans, coverage goals, and sign-off criteria.
• Ability to work independently, take ownership of ambiguous problems, and drive cross-functional investigations.
• Strong communication skills and the ability to collaborate across architecture, design, DV, emulation, firmware, software, package, and product engineering teams.

Nice To Haves

• Experience with both pre-silicon and post-silicon validation.
• Experience with Cadence Palladium or another hardware emulation platform.
• Experience reproducing silicon failures in simulation or emulation environments.
• Experience with Top-level DV, SystemVerilog, UVM, assertions, coverage, or waveform-based debug.
• Experience bringing up first silicon or leading complex silicon-debug activities.
• Experience validating HBM, DDR, PCIe, CXL, Ethernet, die-to-die interfaces, coherent interconnects, or high-speed SerDes.
• Experience with multi-die systems, advanced packaging, SiP integration, or package validation.
• Experience validating power, reset, boot, clocking, thermal, or reliability behavior.
• Experience with error injection, fault handling, recovery flows, or resilience validation.
• Familiarity with JTAG, trace infrastructure, oscilloscopes, logic analyzers, protocol analyzers, and other lab equipment.
• Experience building validation automation, regression infrastructure, dashboards, or failure-analysis tools.
• Experience validating high-performance compute, GPU, AI, or machine-learning silicon.

Responsibilities

• Own silicon bring-up and validation activities from first power-on through feature validation, characterization, qualification, and production readiness.
• Develop and execute validation plans for chip-level and SiP-level functionality, performance, reliability, and system behavior.
• Validate power-up, initialization, boot, reset, recovery, power-management, and error-handling flows.
• Validate compute, memory, interconnect, data-movement, high-speed interface, and package-level functionality.
• Create and execute high-stress workloads that exercise bandwidth, latency, concurrency, coherency, error handling, and long-duration operation.
• Work across Top-level DV, Palladium emulation, lab validation, and package validation to shift validation left and improve correlation between environments.
• Reuse and adapt validation scenarios across simulation, emulation, and silicon where practical.
• Bring up complex hardware and debug failures using registers, logs, traces, waveforms, firmware output, diagnostics, protocol analyzers, and lab equipment.
• Analyze failures across RTL, firmware, drivers, software, board, package, and silicon boundaries.
• Work closely with firmware teams to debug low-level software and firmware interactions with the hardware.
• Review firmware, embedded software, drivers, and diagnostic code as part of failure analysis, without being responsible for their primary development.
• Collaborate with architecture and design teams to understand intended behavior, microarchitecture, performance expectations, and available debug mechanisms.
• Collaborate with DV and emulation engineers to reproduce silicon issues in pre-silicon environments and identify issues before silicon arrives.
• Define validation, observability, and debug requirements needed for effective silicon and SiP-level troubleshooting.
• Support package-level validation, including connectivity, power, reset, signal integrity, thermal behavior, and die-to-die interactions.
• Drive root-cause investigations and coordinate cross-functional debug until issues are understood, contained, and resolved.
• Develop scripts, test infrastructure, automation, and data-analysis capabilities that improve validation execution and failure triage.
• Track validation coverage, execution status, failures, risks, and readiness against product milestones.
• Improve SiP V&V methodology, automation, debug capability, and overall engineering productivity.

Benefits

• Company subsidized Health, Dental, Vision, and Life insurance
• Pre-tax Health Savings Accounts with generous company contribution
• 4 weeks paid time off (accrued)
• 12 company holidays
• 3 weeks remote/flexible work per year
• Up to 12 weeks of paid parental leave
• $1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities
• Team Lunches, quarterly off-sites, and regular town halls
• 401K and/or Roth IRA, with 5% company contribution
• Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses
• $50 per month to use on the perks you care about most
• Home-tech setup
• Remote wifi expense reimbursement

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Education Level: Associate degree