Silicon Design Engineer

Advanced Micro Devices, Inc•San Jose, CA

15h•Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification. THE PERSON: The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and other aspects of verification such as performance verification, power aware verification. You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Requirements

Project level experience with design concepts and RTL implementation for same
Good understanding of computer organization/architecture and digital logic fundamental's
Knowledge of object oriented concepts and programming languages like System Verilog, C++
Hands on Python scripting for automation
Masters degree in computer engineering/Electrical Engineering

Nice To Haves

Prior design/verification industry experience is a plus with hands on experience on UVM

Responsibilities

Work with senior verification engineers and create test plans for complex IP designs.
Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner.
Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
Debug tests with design engineers to deliver functionally correct design blocks and close the coverage.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design
Responsible for verification quality metrics like pass rates, code coverage and functional coverage