Silicon Packaging Design Engineer

Intel Corporation•Hillsboro, OR

1d•$105,650 - $172,860•Onsite

About The Position

As an integral part of Intel's new Integrated Device Manufacturer 2.0 (IDM2.0) strategy, we are establishing Foundry Services (FS), a fully vertical, stand-alone foundry business, reporting directly to the CEO. Foundry Services will be a world-class foundry business and major provider of US and European based capacity to serve customers globally. Foundry Services will be differentiated from other foundries with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, and a world-class IP portfolio that customers can choose from, including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP's, along with Arm and RISC-V ecosystem IPs. Foundry Services will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. The Role and Impact As a Silicon Packaging Design Engineer, you will play a critical role in the development of advanced substrate designs that drive Intel's innovation and technological leadership. This position offers a unique opportunity to contribute to cutting-edge technologies by managing the end-to-end development process of substrate designs, from concept to tapeout. You will collaborate with silicon and hardware teams to optimize design performance, cost efficiency, and manufacturability, ensuring Intel remains at the forefront of high-performance applications. Your contributions will directly impact Intel's ability to deliver world-class solutions that address global challenges in computing.

Requirements

Bachelor's or Master's degree in Electrical, Mechanical Engineering or related field with 1 year of experience.
Experience in Package design tools such as Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
Experience in Physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversions.
Experience in Microelectronic package or PCB physical layout design and the associated manufacturing processes.

Nice To Haves

Experience in microelectronic package substrate design, package I/O routing, or technology development.
Familiarity with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
Analytical and problem-solving skills, including debugging and providing innovative solutions.
Experience with scripting using Python, VB, C, or similar languages.

Responsibilities

Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
Conduct substrate fit and routing studies to establish design, performance, and cost tradeoffs.
Define and implement substrate design rules, conducting internal and external reviews to maintain quality standards.
Analyze data, resolve Design Rule Checks (DRCs), and optimize designs for manufacturability and performance.
Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
Complete documentation and collateral into the product lifecycle management system of record.