Signal/Power Integrity Hardware Engineer (Onsite)

Cisco•San Jose, CA

2d•$110,400 - $183,600•Onsite

About The Position

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. The Cisco Service Provider SI team is seeking a Signal Integrity Engineer for the design and analysis of high-speed components, interfaces, and power distribution network. As a member of the Service Provider SI team, you will help develop the Next Generations of Cisco Switch products, be a part of the definition and design of current and next generation ASIC, package, printed circuit board (PCB), and system interconnect. You will be working in a larger team working closely with system architects, logic designers, ASIC engineers, package engineers, and versatile and knowledgeable SI/PI engineers in the creation of next-generation networking products.

Requirements

Bachelors +2 years of relevant experience or Masters +0 years of relevant experience.
Knowledge of applying EE fundamentals, EM theory, and coupling mechanisms in circuit or system design, analysis, or troubleshooting.
Understanding of transmission line theory, simulation, channel modeling & signal, and power integrity concepts.
Lab and measurement experience to include configuring and interpreting measurements from VNA, TDR, and oscilloscopes.

Nice To Haves

Tools knowledge with tools such as HFSS, ADS, Matlab, Cadence PowerSI/DC, Allegro, Simbeor, and HSpice.
Experience with 3-D field solvers and PI (Power Integrity) simulation tools such as PowerSI/DC.
Self-motivation, collaboration, effective communication, and a desire to innovate.
Working experience with high-speed NRZ and PAM4 SerDes, as well as high-speed PCB/package development and PI analysis.
Knowledge of optical transceiver module types, form factors, and requirements.
Masters or PhD in Electrical Engineering.

Responsibilities

High-speed link modeling and simulation, including high-speed I/O, IC package, and system interconnections.
Modeling and analyzing power delivery networks.
Electromagnetic modeling of complex 3-dimensional structures.
Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs.
Write signal integrity design guidelines, test plan, and test report.
Decide appropriate PCB material, stack-up, and work with vendors to address any DFM issues.
Support prototype function bring-up, validation, and troubleshooting.
Address signal integrity challenges on system high-speed interconnections, clock, power, etc.
Work closely with other hardware function teams including HW design, eCAD, Mechanical, Power, EMC, and Diag to deliver first-class products.
Contribute to the overall SI/PI technology roadmap, evaluating new tools, techniques, and design approaches to maintain a competitive edge.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (Non-exempt employees)
flexible vacation time off program (Exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)