Signal Integrity Validation Internship (Summer 2025)

Cadence Design Systems • San Jose, CA

1d • Onsite

About The Position

The Cadence Silicon Solutions Group (SSG) is seeking students for its R&D teams in San Jose or Austin for the Summer 2025 internship program. This internship offers an opportunity to work at a world leader in computational software, semiconductor design IP, and system verification hardware. Interns will be trained, mentored, and encouraged to use their creative talents to gain practical work experience and make meaningful technical contributions. The work is integral to the company's success and the advancement of the industry.

Requirements

• Currently enrolled in MSEE or equivalent.
• Understanding of electro-magnetic principles for digital signal integrity.
• Experience with signal integrity and electro-magnetic simulation/analysis tools such as Ansys HFSS and Designer, CST Microwave.
• Experience with signal integrity measurements and debugging with TDR, VNA, pattern generators, error detectors and similar measurement equipment.
• Understanding of frequency-domain and time-domain component and circuit characterization.
• Understanding of test and calibration methods.

Nice To Haves

• Experience in component design and application of high-speed cables/connectors into communications equipment is a plus.
• Experience with Cadence tools, Matlab, ADS, and HSPICE is a plus.

Responsibilities

• Performing modeling and simulation of high-speed interface interconnects/channel.
• Working in the lab to perform measurements and correlate measurements to simulations.
• Working with silicon designers, platform designers, package designers, and electrical validation teams to support interconnect and interface performance requirements.
• Contributing to package and platform design guideline development.
• Reviewing and evaluating package and board design and providing review feedback.
• Electrical modeling and simulation of high-speed IO interconnects, such as DDR.
• Development of package and platform design guidelines.
• Definition and evaluation of circuit design features required to support interconnect performance requirements.
• Creation of signal measurement test plans and review of measurement results.
• Correlation of measurements to simulations, and modification of models as required.
• Support signal integrity tool and methodology development.

Benefits

• paid vacation
• paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

What This Job Offers

• Career Level: Intern
• Number of Employees: 5,001-10,000 employees