Signal Integrity Lead

Qualcomm•San Diego, CA

6d•$221,100 - $331,700

About The Position

The Qualcomm Data Center team is developing high-performance, energy-efficient server solutions for data center applications. We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work. Our Mission: We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing reference platforms based on Qualcomm's Snapdragon SoC, delivering a comprehensive solution that includes hardware, software, reference designs, user guides, SDKs, and more. Position: Signal Integrity Lead. We are seeking a Signal Integrity Lead to provide technical and people leadership across Qualcomm's data center server platforms. In this role, you will lead and grow a team of signal integrity engineers while collaborating closely with platform, silicon, packaging, firmware, and component engineering teams. You will be responsible for establishing SI methodology, validation strategy, design guidelines, and product-level signoff criteria across memory and SerDes interfaces, package-to-board integration, PCBs, cables, and system interconnects. The role requires close collaboration with silicon and package design organizations to assess die/package SI solutions and ensure successful integration into Qualcomm server products.

Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in signal integrity analysis, simulation, and validation of high-speed digital systems.
Experience managing a signal integrity engineering team.
Strong knowledge of SI fundamentals, including transmission line theory, channel analysis, crosstalk, S-parameters, jitter analysis, and system-level performance optimization.
Working knowledge of power integrity concepts, including PDN analysis and EMIR considerations.
Expertise in DDR5/LPDDR6 interfaces and/or high-speed SerDes technologies such as PCIe, CXL, Ethernet, and UCIe.
Experience developing and correlating SI methodologies from package through system-level implementation and laboratory validation.
Proficiency with simulation tools such as ANSYS HFSS, Cadence Sigrity, Dassault Systèmes CST, Keysight ADS, and Synopsys HSPICE.
Hands-on experience creating SI models and performing both frequency-domain and time-domain simulations.
Proficiency in Unix/Linux environments and scripting for EDA tool automation.
Strong understanding of packaging and PCB technologies, design methodologies, and manufacturing processes.
Familiarity with advanced packaging technologies, including CoWoS, InFO, EMIB, RDL, and other 2.5D/3D integration approaches.
Experience with electrical validation and compliance testing using oscilloscopes, VNAs, TDR systems, protocol analyzers, traffic generators, and related laboratory equipment.
Demonstrated success building and scaling technical teams, hiring talent, and establishing engineering best practices.
Strong written, verbal, and presentation skills.
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Systems Engineering or related work experience.
Master's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Systems Engineering or related work experience.
PhD in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.

Nice To Haves

Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
15+ years of experience in signal integrity analysis, simulation, validation, and architecture of high-speed systems.
In-depth understanding of computational electromagnetics, signal integrity architecture, and transmission line theory.
Expertise in DDR5 and LPDDR6 timing budgets, PHY design, link analysis, and margin characterization.
Experience with PCIe Gen 6+, CXL, Ethernet, UCIe, and 112Gbps+ serial communication channels.
Experience with package and PCB design tools such as Cadence Allegro.
Proficiency in MATLAB, Python, Perl, or comparable scripting and automation environments.
Experience developing server, AI, HPC, data center, or rack-scale computing platforms.

Responsibilities

Lead, develop, and grow the Signal Integrity team, including hiring, coaching, career development, performance management, and resource planning across multiple programs.
Define signal integrity strategy, methodology, and best practices across Qualcomm data center products.
Collaborate with SoC, applications engineering, packaging, and system design teams to develop system interconnect solutions that meet performance, reliability, and scalability requirements.
Collaborate with silicon and package design teams to review and validate die/package signal integrity solutions and approve their integration into the final server product.
Provide guidance and feedback on silicon timing, bump/RDL implementation, package pinout, PCB specifications, connector selection, and channel architecture.
Establish design rules, signoff criteria, correlation plans, and validation processes for high-speed interfaces.
Develop customer guidelines and define model formats and interfaces for simulation and system integration.
Lead the development of SI models, simulation frameworks, and analysis flows across memory and high-speed serial interfaces.
Assess early SI analysis of advanced packaging technologies, including 2.5D and 3D integration structures, and establish system-level integration guidelines.
Drive system-level SI architecture spanning package-to-board interfaces, PCB, connectors, cables, chassis, and future rack-level interconnects.
Update and automate design and analysis flows to improve productivity, accuracy, and scalability.
Partner with cross-functional teams to resolve complex SI issues and drive technical decision-making throughout product development.
Prepare and present technical documentation, design reviews, and recommendations to engineering teams, senior leadership, customers, and suppliers.