Serdes Characterization & Post-Silicon Validation Engineer

K2 Space•Los Angeles, CA

About The Position

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply. About the Role We are looking for a hands-on SerDes Characterization & Post-Silicon Validation Engineer to bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs. You will work closely with SerDes/IP, mixed-signal, digital, firmware, SI/PI, package, board, and systems teams to take high-speed interfaces from first silicon through product integration and system-level operation. You will also help build our high-speed test and validation capability from the ground up.

Requirements

BS/MS in Electrical Engineering, Computer Engineering, or related field.
5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
Deep hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
Experience with eye diagrams, jitter decomposition, bathtub curves, BER testing, stressed-eye testing, and receiver sensitivity characterization.
Strong understanding of package/PCB channels, insertion/return loss, crosstalk, reflections, and channel de-embedding.
Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces.
Strong debugging skills across silicon, package, PCB, firmware, and system boundaries.
Ability to work closely with SerDes IP/design, SI, package, board, firmware, and digital teams.

Nice To Haves

Experience with 112G+ PAM4 SerDes characterization and validation.
Experience with Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces.
Experience with compliance testing and high-speed interface standards.
Familiarity with SerDes behavioral/channel models and simulation-to-measurement correlation.
Experience with SerDes IP integration and validation from third-party IP vendors.
Experience with advanced package and high-loss PCB channels.
Familiarity with high-speed clocking, PLLs, reference-clock jitter, and power-supply noise effects on SerDes performance.
Experience with automated PVT characterization and large-scale measurement data analysis.

Responsibilities

Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes, including 112G-class interfaces.
Develop and execute electrical characterization plans across lanes, data rates, voltage, temperature, channels, and operating conditions.
Characterize TX eye quality, jitter, output amplitude, linearity, equalization, RX sensitivity, BER, bathtub curves, CDR performance, and link margin.
Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior.
Perform BER and stress testing across representative and worst-case channels.
Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.
Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.
Partner with firmware and digital teams on SerDes configuration, initialization, diagnostics, adaptation, and system-level link bring-up.
Develop automated characterization and regression environments for instrument control, data collection, analysis, and reporting.
Support the transition from chip-level SerDes characterization to product integration and system-level validation.
Contribute to building the high-speed validation lab, equipment, test infrastructure, measurement methodology, and automation from the ground up.