Senior Post-Silicon Validation Engineer

K2 Space • Seattle, WA

1d

About The Position

K2 is seeking a hands-on Senior Post-Silicon Validation Engineer to take ownership of silicon bring-up, characterization, and system-level validation for complex mixed-signal SoCs. This role is crucial for ensuring a seamless transition from validated silicon to product integration. The successful candidate will define the validation strategy, establish our test and validation capabilities from the ground up, and lead the execution from the initial silicon stage through to product readiness. This is an opportunity to contribute to a high-growth, Series D-funded company building the largest and highest-power satellites ever flown.

Requirements

• BS/MS in Electrical Engineering, Computer Engineering, or equivalent experience.
• 5+ years of post-silicon validation, SoC bring-up, silicon characterization, or related experience.
• Hands-on experience bringing up complex mixed-signal SoCs/ASICs and transitioning silicon into product/system integration.
• Hands-on experience with lab test and measurement equipment, including oscilloscopes, spectrum/signal analyzers, vector signal generators, network analyzers, logic analyzers, power supplies, and related RF/mixed-signal instrumentation.
• Strong understanding of SoC architecture and working knowledge of RF/analog and mixed-signal circuits.
• Strong hardware/software debug skills spanning silicon, RTL, firmware, board, and systems.
• Experience building silicon validation labs, test infrastructure, and automated measurement environments.
• Experience validating DSP, calibration, or signal-processing functionality in silicon.
• Strong Python/scripting skills for lab automation, instrumentation, and data analysis.
• Experience with embedded C/C++, JTAG, SPI, UART, and register-level debug.
• Ability to lead cross-functional bring-up while remaining deeply hands-on in the lab.

Nice To Haves

• RF SoC and RF/analog characterization experience.
• ADC/DAC, PLL, RF transceiver, or high-speed SerDes/JESD validation experience.
• FPGA prototyping and RISC-V/ARM SoC experience.

Responsibilities

• Own post-silicon validation strategy, test planning, execution, coverage, and sign-off.
• Lead first silicon bring-up across power, clocks, debug interfaces, processor/memory subsystems, peripherals, and high-speed interfaces.
• Define and execute the validation strategy and readiness criteria needed to enable product integration, ensuring silicon, firmware, test infrastructure, and system interfaces are ready for integration.
• Own system-level test planning and execution, including functional, performance, stress, and corner-case testing.
• Help build the test and validation lab from the ground up, including equipment, infrastructure, test setups, and automated characterization and regression environments.
• Partner with RF/analog and mixed-signal designers on characterization of RF chains, PLLs, ADCs/DACs, clocking, and power.
• Work closely with systems/DSP teams to validate DSP and calibration algorithms on silicon and correlate measured performance with models and simulations.
• Partner with FPGA, firmware, RTL/DV, hardware, and systems teams to accelerate silicon bring-up, enable product integration, and drive end-to-end validation.
• Drive cross-functional debug across silicon, firmware, RTL, package, board, and system boundaries.
• Build reusable automation for instrumentation control, data collection, analysis, regression, and reporting.
• Drive silicon issues from discovery through root cause, workaround, and resolution.

Benefits

• Base salary range for this role is $170,000 – $250,000 + equity in the company
• Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
• Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

What This Job Offers

• Job Type: Full-time
• Career Level: Senior