Senior Yield Analysis Engineer

Samsung•Austin, TX

3d•Onsite

About The Position

As a Yield Analysis Engineer at Samsung Austin Semiconductor, you will own key high-volume products across all tech nodes. The individual will collaborate with customer and internal teams to monitor health of the line and trace yield deviations to closure. The individual will help drive for defense lines to ensure traced yield deviations do not have recurrence.

Requirements

BS or MS in Electrical Engineering, Physics, or Chemical Engineering preferred.
A minimum of four years of experience as a Device and/or Process Engineer, with knowledge of semiconductor processes, coding, process integration, and device physics, is required.

Responsibilities

Yield event closure and defense line: Drive detection source to closure by confirmation of defense line effectiveness.
Customer yield management: Prepare customer material set, cross-functional alignment on overall message, and active meeting participation required.
Commonality: Daily wafer testing (EDS) map review and yield summary, analytical deep dives (root cause for bin and zonal shifts), dog tool analysis, and integrated issues resulting from multiple change points to identify source of yield degradation or opportunity.
Change point analyses: YA is responsible for all change point analyses for spec release for both EDS and FT yield. This includes deep dives of change points to provide specific bin / zonal issues with failing change point proposals.