Experienced Yield Analysis Engineer

Samsung•Austin, TX

1d•Onsite

About The Position

Samsung Austin Semiconductor is seeking a highly analytical and detail-oriented Yield and Process Control and Investigation(PCI) Engineer to join our semiconductor manufacturing team. In this role, you will be critical in monitoring wafer manufacturing processes, driving yield enhancement, and investigating process excursions. You will utilize advanced statistical process control (SPC), defect inspection data, and parametric testing results to identify root causes of yield limiters. Working closely with cross-functional teams—including Process, Equipment, and Integration engineering—you will implement robust solutions to ensure process stability, minimize defects, and maximize product yield.

Requirements

B.E. M.Sc. in Electrical Engineering, Materials Science, Physics, Applied Physics, or related field.
Understanding of semiconductor device physics and CMOS fabrication processes (Lithography, Etch, Thin Films, CMP, Diffusion, Implant).
Understanding of electrical parametric testing, defect inspection mechanisms.
Strong technical writing and presentation skills to effectively communicate technical data to diverse audiences.
Ability to thrive in a fast-paced, 24/7 cleanroom manufacturing environment.
Capable of managing multiple high-priority investigations simultaneously while collaborating seamlessly with cross-functional teams.
Proactive and organized with excellent verbal and written communication skills for reporting to "home teams" and global stakeholders.
Cross-functional leadership and communication.
Exceptional analytical problem-solving skills with a proven track record of resolving complex process excursions.
Applicants must be authorized to access such information or eligible for government authorization.

Responsibilities

Develop, implement, and validate complex yield prediction models that correlate inline metrology, defect inspection data and FDC(Fault Detection and Classification) metrics.
Forecast yield trajectories for ramping and mature technology nodes, proactively identifying yield risk areas before wafers reach EDS test.
Drive end-to-end yield performance across wafer sort, parametric, and final tests by performing advanced data mining and statistical analysis to identify yield limiters and correlate detractors with electrical, inline, and defect data to implement improvement actions.
Lead root cause analysis through structured methodologies, correlating electrical signatures with physical defects via EFA/PFA partnerships, and collaborating with Design and Product teams to eliminate layout-dependent yield limiters before ramping.
Apply advanced data science techniques and machine learning to build sophisticated yield models and automated analytics pipelines using Python, JMP, and SQL to enhance yield dataset analysis.
Define strategic roadmaps, KPIs, and improvement strategies, while managing major yield excursions, mentoring junior engineers, and communicating yield health and risks to executive leadership.