Senior Validation Engineer

Microsoft • Mountain View, CA

1d • $119,800 - $261,000

About The Position

The Artificial Intelligence Silicon Engineering team is seeking a Senior Validation Engineer for the Post-Silicon Validation team in Microsoft’s Artificial Intelligence System on Chip (AISoC) Silicon organization. The role focuses on delivering high-quality, cutting-edge AI silicon designs and requires expertise in one or more validation domains, including functional, electrical, high-speed interfaces, memory, power/performance, debug/bring-up, or tool development.

The engineer develops validation strategies, requirements, environments, tools, and methodologies; writes and implements test plans; and executes post-silicon testing, triage, and debug. The role also contributes to pre-silicon verification plans, tests, and debug. It involves collaboration with architects, logic designers, verification engineers, other post-silicon validators, IP providers, and tool providers, as well as providing technical guidance and mentorship to other engineers.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a master's degree in one of these fields and at least 4 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Ability to satisfy export-control eligibility requirements for access to controlled information, including providing proof of citizenship, U.S. residency, or other protected status and verifying citizenship or status with acceptable documentation.

Nice To Haves

• Demonstrated success in running cross-disciplinary taskforces.
• Verification, logic design, or validation experience as part of a CPU, SoC, and/or IP development team.
• Leadership skills.
• Experience with high-speed I/O, such as Ethernet or PCIe.
• Understanding of board-level schematics.
• Understanding of system-level software and firmware.
• Demonstrated success in hardware/software debug efforts.
• Expertise debugging silicon failures using on-chip debug features such as trace or JTAG, and test equipment such as protocol analyzers, bit error rate testers, logic analyzers, and high-speed oscilloscopes.

Responsibilities

• Develop validation strategies, requirements, environments, tools, and methodologies, including debug board and hardware/software requirements.
• Write test plans and implement them by developing test content, scripts, tools, and other verification collateral.
• Execute post-silicon content, triage results, and debug failures.
• Learn and adapt in a complex and dynamic environment.
• Work with partners to improve designs, validation plans, collateral, and methodologies to prevent, reduce, or find bugs sooner, more easily, or more reliably.
• Provide technical guidance, coaching, and mentorship to other engineers in areas of expertise.
• Collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers.
• Deliver high-quality results on schedule.
• Provide technical leadership with respect and integrity.
• Apply expertise to pre-silicon verification plans, tests, and debug in the engineer’s area.

Benefits

• Certain roles may be eligible for benefits and other compensation; additional benefits and pay information is available through the Microsoft careers website.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior