Senior UVM Digital Verification Engineer

Draper•Cambridge, MA

3d•$82,300 - $220,000•Onsite

About The Position

Draper’s Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications. You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.

Requirements

5-7 years experience in systems analysis or related.
Experience in integrating descriptive modeling tools with other simulation tools.
Excellent mathematical skills.
Thorough understanding of engineering theories and procedures.
Ability to collaborate within a diverse and multidisciplinary team.
Excellent verbal and written communication skills.
Excellent organizational skills and attention to detail.
Excellent time management skills with the proven ability to meet deadlines.
Demonstrated knowledge of multiple problem domains, with ability to quickly become knowledgeable in new domains.
Identify and develop relevant modeling and analysis techniques, and develop or integrate multi-domain qualitative models.
Ability to present results that support system-level analysis, performance trade-offs, and decision-making is critical, thus communications and interpersonal skills are highly valued in this role.
The ability to communicate technical concepts effectively with customers, engineers, managers, and other stakeholders of all relevant disciplines.
Flexibility to multi-task and adapt to evolving priorities.
Fluent in System Verilog including SVA
Recent experience with UVM/UVMF
Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
Familiarity with at least one IEEE bus standard
Experience with DDR3/DDR4, Amba Axi protocols
Firm grasp of constrained-random testing and coverage-driven verification
Experience with formal analysis
Practice using Python, Perl, Bash or other scripting languages
Ability to work in a Linux environment
Strong analysis and problem-solving skills
Applicants selected for this position will have or be able to obtain and maintain a government security clearance.

Nice To Haves

Master's degree preferred.

Responsibilities

Performs analysis approaches for a particular problem and independently execute assignments.
Independently execute system engineering lifecycle assignments; concept and architecture design, integration, testing and operation.
Drive solutions to complex problems with limited direction – contribute to task planning and test development, propose ways forward, and adapt appropriately to changes in program requirements
Demonstrated ability to lead small teams (fewer than five people). Seeks to align team towards program goals and builds trust within the team.
Able to provide insight and suggest design modifications based on analysis outcomes, and to apply analysis techniques across a range of technical challenges.
Identify program/system-level technical risks and develop and execute mitigation strategies for them.
Actively mentor less experienced engineers and provide thoughtful, constructive feedback.
Work in a collaborative multidisciplinary environment including stakeholders and external partners.
Contribute to translation of requirements into technical and architectural decisions.
Develop verification and test plans
Develop UVM Agents for proprietary buses
Instantiate VIPs for industry standard buses
Work in both block-level/chip-level UVM testbench environment
Work with RTL designers to resolve simulation issues
Implement cover groups according to design requirements
Work on code and functional coverage closures to achieve 100%
Perform code reviews and to mentor junior engineers in the group