Digital Verification Engineer

Nexthop Systems Inc•Santa Clara, CA

2d•Onsite

About The Position

At Nexthop AI, the correctness of our digital logic is non-negotiable — a single functional escape in an FPGA or ASIC can compromise an entire switching platform once it ships. We are looking for a Digital Verification Engineer to own the verification environments and test suites that prove our digital subsystems behave exactly as designed. Sitting within the Hardware Design organization, you'll work shoulder-to-shoulder with RTL designers and firmware engineers to catch bugs in simulation — long before they reach silicon, a board, or a customer's rack.

Requirements

3–7 years of digital verification experience on FPGA or ASIC designs.
Proficiency in Verilog (SystemVerilog strongly preferred).
Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog.
Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions.
BS/MS in Electrical Engineering, Computer Engineering, or a related field.

Nice To Haves

Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).
Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.
Structured verification methodology experience (UVM or equivalent).
Familiarity with networking / switching datapaths or high-speed interfaces.

Responsibilities

Own the testbench: Design, build, and maintain the verification environments for our digital subsystems — from block level through full-chip / subsystem integration — for both FPGA and ASIC targets.
Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches.
Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.
Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior.
Define functional and code-coverage goals and drive them to closure — identifying coverage holes and writing the stimulus to fill them.
Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.
Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix.
Stand up and maintain automated regression suites — keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change.
Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design–debug loop.
Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware.
Partner with firmware / software engineers during system bring-up — validating register maps, interfaces, and boot / init sequences across the HW/SW boundary.
Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.