Senior Technical Staff Engineer - Process (Foundry)
About The Position
We are seeking a highly motivated Technical Staff Engineer - Process (Foundry) to join our Technology Development Group in San Jose, CA. This position is part of the FPGA (Field Programmable Gate Array) Business Unit, which is a leader in research, development, and manufacturing of highly reliable non-volatile Field Programmable Gate Arrays. The successful candidate will be responsible for coordinating and communicating with the Foundry, defining process flow and mask list, coordinating test chip/shuttle tape out, defining TD test chips, coordinating test chip layout, and coordinating with UMC/SST/design/IP vendor on test chip coverage versus shuttle area. They will also be responsible for test chip Si and process learning, Si Etest/data review, eNVM IP Si data analysis, coordinating product tape out, Si learning, yield, and qual, and process tuning as needed for device, yield, and qual. Additionally, the role involves assisting with all yield analysis and FAs.
Requirements
- BS in Engineering or a related technical discipline
- 10+ years of experience with 5+ years in the semiconductor industry
- Experience with Foundry interaction and communication
- Familiar with design rules, mask, and tape-out flow
- Knowledge of semiconductor device physics
- Strong data analysis skills
- Experience in test chip design and characterization
- Good understanding of failure analysis and yield improvement
- Demonstrated adaptability and flexibility in a fast-paced, evolving environment
- Excellent verbal and written communication skills, with the ability to convey complex technical concepts to cross-functional teams
- Proactive problem-solving attitude and a willingness to take initiative in addressing technical challenges
Responsibilities
- Coordinate and communication with the Foundry
- Define process flow and mask list
- Coordinate test chip/shuttle tape out
- Define TD test chips
- Coordinate test chip layout
- Coordinate with UMC/SST/design/IP vendor on test chip coverage versus shuttle area
- Coordinate test chip Si and process learning
- Si Etest/data review
- eNVM IP Si data analysis
- Coordinate product tape out, Si learning, yield, and qual
- Process tuning as needed for device, yield, and qual
- Assist with all yield analysis and FAs
Benefits
- Health benefits that begin day one
- Retirement savings plans
- Industry leading ESPP program with a 2 year look back feature
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What This Job Offers
Job Type
Full-time
Career Level
Senior
