Senior Technical Program Manager – Silicon Co-Design

NVIDIA•Santa Clara, CA

1d•$200,000 - $322,000•Onsite

About The Position

NVIDIA's Silicon Co-Design Group (SCG) operates at the intersection of architecture, silicon, systems, and manufacturing, where high-level engineering judgment leads to large-scale product outcomes. We are seeking a Senior TPM who will not only lead programs but also shape them. This individual will have a history of owning SoC programs from architecture through tape-out, bring-up, and productization, focusing on outcomes, schedules, and trade-offs rather than just coordinating meetings. The ideal candidate combines deep hands-on knowledge of bring-up and validation with the ability to identify integration risks across silicon, systems, and software. They will drive alignment across engineering, operations, and product, making difficult decisions and operating effectively even when requirements and architecture are in flux. This role requires identifying dependencies and misalignment early, mitigating risks with credible plans, and improving organizational processes after each program. Strong understanding of silicon hardware logistics (silicon, boards, peripherals) is essential to ensure validation and bring-up remain unblocked. Exceptional candidates will also leverage AI deliberately, possessing hands-on experience with AI-powered program management tools for automated status, risk, and dependency signals, and can discern effective tools from those that add noise. This role requires on-site teamwork in Santa Clara, a minimum of three days per week.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent experience); a master’s is a plus
12+ years in technical roles, with at least 5 years in technical program management — ideally driving SoC programs from bring-up through productization
Deep, hands-on understanding of SoC bring-up, validation, and productization — you know the stages, what each involves, and what can go wrong
Ability to work across the silicon–system–software boundary — enough depth in each area to spot integration risks and drive fixes without having to be the expert on every technical question
Proven track record to run fast development cycles in uncertainty — you develop transparency instead of waiting for it
Communication that is precise, direct, and right-sized for the audience
On-site in Santa Clara, CA, a minimum of three days per week

Nice To Haves

Used AI-style program management tools (e.g., automated status, risk flagging, dependency tracking) and can tell which tools help outcomes vs add noise
Experience working with AI/ML teams on inference infrastructure and aligning multi-functional work with go-to-market timing for AI-accelerated products
Experience with AI-assisted logistics tracking to speed bring-up and reduce manual efforts, including where those approaches stop being reliable
Can evaluate and help roll out new AI productivity tools (coding assistants, automated documentation) and make a clear case for what actually improves engineering velocity

Responsibilities

Own program outcomes end-to-end — define and manage schedules, surface dependencies before they block work, and drive multi-functional alignment from architecture review through tape-out and bring-up; you’re accountable for delivery, not only oversight.
Lead through design complexity — take part in critical design reviews, flag scope risks early, resolve them with minimal disruption, and make trade-off calls others will depend on.
Be the connective tissue — act as the main technical link among silicon, systems, software, operations, and marketing; keep teams aligned on program goals and GTM needs, and catch misalignment before it hurts the program.
Drive risk to closure — find technical and schedule risks early, build mitigations with engineering, and move work forward with clarity and context, not only status.
Raise the execution bar — capture lessons from finished programs and put in place process changes that measurably improve speed, quality, and predictability on later programs.
Handle silicon hardware logistics — coordinate movement, tracking, and availability of silicon, boards, and peripherals so validation and bring-up stay unblocked.