Senior Technical Program Manager - AI Acceleration

NVIDIA•Santa Clara, CA

1d•$168,000 - $322,000

About The Position

We are building the next generation of AI-powered simulation tools to accelerate hardware and silicon development. AI is reshaping how engineering teams operate, and we are investing in solutions that bring chatbots, agents, and assistant intelligence into the core of hardware workflows. As a Senior Technical Program Manager, you will play a critical role in turning this vision into reality — driving multi-functional programs, scaling systems, and delivering AI capabilities that transform how silicon is designed, verified, and brought to production. This role will also help enable AI productivity across hardware teams by making both internal and third-party AI tools available, understanding user requirements, and translating feedback back to internal platform teams and external partners. Spanning ASIC and research org, this role drives execution in close collaboration with engineers across all teams. We emphasize having influence over technical direction, not just performing tasks or tracking metrics. You should consider yourself an expert in chip design workflows and AI — or demonstrate a strong willingness to learn. Our mission is to enable NVIDIA to design and deliver world-class silicon faster than ever using AI while ensuring performance, efficiency, and resilience.

Requirements

Bachelor’s degree or equivalent experience in Computer Science, Electrical Engineering, or a related field, with proven experience leading complex, multi-functional technical programs in AI, silicon, or infrastructure
10+ years of technical program management spanning AI and ASIC chip design
Strong understanding of RTL design, simulation, and formal verification, as well as software engineering fundamentals, system architecture, and scalable infrastructure
Hands-on experience building, deploying, integrating, or enabling AI agents, LLM-powered systems, or AI productivity tools in real-world engineering workflows
Proven ability to collaborate deeply with engineering teams and influence technical decisions, architecture, prioritization, and trade-offs
Experience driving programs from concept through production, including planning, execution, risk management, team alignment, and delivery at scale
Ability to gather, synthesize, and prioritize requirements from technical users, and communicate them clearly to internal engineering teams and external partners
Excellent communication and leadership, with the ability to translate complex technical concepts into clear program direction and updates

Nice To Haves

Hands-on experience in hardware or silicon development environments, understanding RTL, verification, and pre-silicon workflows
Experience evaluating, integrating, or deploying third-party tools into enterprise engineering environments
Familiarity with cloud-scale infrastructure, orchestration systems, and data pipelines for AI applications
Experience with cross-geography coordination and leading large teams or projects spanning multiple sites

Responsibilities

Lead end-to-end planning and execution of AI for Chip Design initiatives, ensuring timely, on-scope, and scalable delivery
Define program plans and timelines for AI capabilities, tracking progress, partnership status, risks, opportunities, and reporting status to leadership
Lead technical discussions between AI engineers, hardware teams, platform groups, and third-party tool providers to ensure alignment on requirements, architecture, integration, and delivery expectations
Operationalize the evaluation of both internal and external AI tools, drive their availability and adoption by collaborating with hardware teams, providing guidance, and gathering feedback for continuous improvement
Act as a product and program interface between silicon design teams, internal AI platform teams, and third-party partners, helping prioritize requirements and translate user needs into actionable roadmaps
Establish and monitor key program metrics to measure execution success, identify bottlenecks, and ensure delivery meets quality, performance, and scalability targets
Serve as the central point of communication for all collaborators, providing clear status updates and insights into dependencies.
Partner with engineering leaders to prioritize initiatives that improve impact for silicon development and hardware workflows