Senior Technical Lead, Signal/Power Integrity Hardware Engineer (Onsite)

Cisco•San Jose, CA

1d•Onsite

About The Position

The Cisco UCS SI team is seeking a Senior Technical Lead, Signal/Power Integrity Engineer for the design and analysis of high-speed interconnects and power distribution networks. As a member of the UCS SI team, you will help develop the next generations of Intel, AMD based Compute Servers for Cisco Blade products, participating in the definition and design of current and next-generation CPUs, ASICs, packages, printed circuit boards (PCBs), and system interconnects. You will be working in a larger team, collaborating closely with Design Hardware Engineers, ECAD, Mechanical, Thermal, Manufacturing, and versatile and knowledgeable SI/PI engineers in the creation of next-generation Compute Server and AI Server products.

Requirements

Bachelors in Electrical Engineering or Physics or equivalent with 11+ years of related experience, or Masters in Electrical Engineering or Physics or equivalent + 7 years of related experience, or PhD in Electrical Engineering or Physics or equivalent + 4 years of related experience.
Experience with EE fundamentals, EM theory, and coupling mechanisms.
Experience with transmission line theory, simulation, channel modeling, and signal and power integrity concepts.
Lab and measurement experience (VNA, TDR, & Scopes).
System level and component level validations.

Nice To Haves

Experience with tools such as ICAT(Intel), Seasim (AMD), HFSS, ADS, MATLAB, Cadence PowerSI/DC, Allegro, Simbeor, and HSpice.
Proficiency with 3-D field solvers and PI (Power Integrity) simulation tools such as PowerSI/DC.
Self-motivation, collaboration, effective communication, and a desire to innovate are important.
Working experience with high-speed DDR links, NRZ and PAM4 SerDes, as well as high-speed PCB/package development and PI analysis, is a plus.
Knowledge of optical transceiver module type

Responsibilities

High-speed link modeling and simulation, including high-speed I/O (DDR, PCIe, CXL, UPI, Ethernet etc.), IC package, and system interconnections.
Modeling and analyzing power delivery networks.
Electromagnetic modeling of complex 3-dimensional structures.
Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs using simulations, system level validations, and statistical analysis.
Write signal integrity design guidelines, test plans, and test reports.
Decide appropriate PCB material, stack-up, and work with vendors to address any DFM (Design for Manufacturability) issues.
Support prototype function bring-up, Bare board and System level validation, and troubleshooting.
Work closely with other hardware function teams including HW design, ECAD, mechanical, power, EMC, and Diagnostics to deliver first-class products.
Lead the investigation and resolution of highly complex, system-level signal and power integrity challenges that span multiple domains (ASIC, package, PCB, system).
Lead comprehensive SI/PI design reviews, providing expert guidance and ensuring adherence to stringent performance and reliability targets.
Drives innovation on large features from technical design through completion and mentor others.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
paid time away
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)