Senior Technical Staff-Design (Signal and Power Integrity)

Microchip Technology Inc.•San Jose, CA

3d•$91,000 - $232,000

About The Position

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products. Microchip Technology Inc. has a Senior Technical Staff -Design (Signal and Power Integrity) opening based in San Jose, CA. The successful candidate will be responsible for developing and driving Signal and Power Integrity methodologies for high-speed FPGA products. You will be working with other SIPI engineers and working with a global cross functional team to provide solutions at a system level for internal and external customers.

Requirements

Bachelor of Science (BS) degree in Electrical Engineering or Electronic --Engineering
15+ years of relevant experience
10+ yeas of practical, hands-on experience directly related to Signal Integrity and Power Integrity (SIPI).
Extensive practical experience in Printed Circuit Board (PCB) design and layout principles.
Robust understanding of system-level SIPI design methodologies and analysis techniques (die-level, package-level, board-level).
Proficiency in analyzing and optimizing signal and power integrity across different levels of integration.
Thorough understanding of PCB manufacturing processes (design to production).
Strong analytical and problem-solving skills.
In-depth understanding of S-Parameter extraction techniques and system-level channel modeling.
Expertise in via modeling, connector Time Domain Reflectometry (TDR) analysis, and stack-up analysis.
Adept at equalization techniques, jitter analysis, eye diagram analysis, and addressing channel impairments (return loss, insertion loss).
Strong, hands-on experience with industry-standard Field Solvers: Ansys HFSS, Ansys Siwave, Mentor Graphics Hyperlynx, and HSPICE, Redhawk
Experience with simulation tools: Keysight ADS and Mentor Graphics Hyperlynx for pre- and post-layout simulation and analysis.
Hands-on experience with Vector Network Analyzers (VNAs), Time Domain Reflectometers (TDRs), Sampling and Real-Time Oscilloscopes, Bit Error Rate Testers (BERTs), de-embedding techniques, and jitter analysis equipment.

Nice To Haves

High-Speed SerDes (Serializer/Deserializer) experience is highly desirable, especially troubleshooting channel-related issues for 32G transceivers and beyond.
Demonstrated experience in resolving SI/PI-related challenges, including Power Delivery Network (PDN) optimization and noise mitigation.
Build and construct system level topologies for co-sims on PDN and transceivers
Experience in performing package analysis and optimization (thermal and mechanical considerations) is a plus.
Experience with IBIS-AMI modeling, validation, and correlation is a significant plus.
Master of Science (MS) degree in a relevant engineering field is preferable.

Responsibilities

Collaborate effectively within a global team environment, demonstrating excellent communication skills (verbal and written).
Possess robust analytical and debugging capabilities for high-speed Signal Integrity and Power Integrity (SIPI) analysis across Die, Package, and Boards.
Understand channel loss mechanisms, interpret and optimize eye diagrams, and apply jitter analysis and mitigation techniques.
Demonstrate a thorough understanding of correlation methodologies and expertise in crosstalk analysis and reduction.
Possess a comprehensive grasp of Power Delivery Network (PDN) design and optimization.
Conduct extensive SIPI simulations (pre-layout and post-layout) to optimize signal integrity and power integrity performance at a system level.
Influence die changes based on simulation results to ensure optimal SIPI performance.
Implement and maintain robust SI/PI strategies throughout the product development lifecycle (die and package).
Proactively identify and address potential SIPI issues early in the design process.
Stay abreast of the latest industry trends, emerging tools, and methodologies in SIPI, PDN design, and SerDes transceiver development.
Provide technical guidance and mentorship to other SIPI engineers within the team.
Develop and refine methodologies for running simulations to ensure robust and reliable PDN systems.
Develop strategies and methodologies to guarantee robust performance of high-speed SerDes transceivers, including equalization techniques and advanced jitter analysis.
Collaborate effectively with external partners, suppliers, and customers on SI/PI-related topics.
Actively contribute to the development of new design methodologies, innovative tools, and streamlined processes to continuously improve SIPI design efficiency and product performance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature.
Benefits of working at Microchip

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