Senior System Level Testability Engineer

NVIDIA•Santa Clara, CA

6d•$196,000 - $310,500•Hybrid

About The Position

NVIDIA’s Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing where first-principles thinking and engineering judgement at the highest level translate directly into product outcomes at scale. Our team gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior System Level Testability Engineer to join our Test, Manufacturability, Reliability & Quality (TMRQ) team. You will define and drive system-level diagnostics, verification, and post-silicon validation for some of the industry's most complex semiconductor chips. You have experience defining SLT production coverage specifications, validating them on silicon, and translating product requirements into effective test coverage. Hands-on lab experience with system-level post-silicon bring-up and debug is required. The exceptional hire continuously improves production workflows and products cross-functionally and uses AI deliberately to drive impact while managing risk.

Requirements

Bachelor’s or Master’s Degree or equivalent in Microelectronics/Electrical/Electronic/Computer Engineering or equivalent experience.
8+ years of relevant industry experience
Strong EE fundamentals, knowledgeable in digital design, signal integrity, statistics, timing analysis, fault analysis, sampling and computer architecture.
Strong data analysis skills. Prior experience working with volume data is a plus.
Validated hands-on lab experience with silicon bring-up and lab debug.
Good understanding of firmware/driver structures and their interaction with HW.
Problem-solving, debugging, analysis, and logical reasoning skills with examples to prove it
Experience with Python, BASH, Linux

Nice To Haves

Exceptional work ethic and up-leveling discussions to solve the real problems
Native use of AI to accelerate production testing and debug workflows
Battle-tested on GPUs, CPUs, AI accelerators, or other large-scale SoCs — you’ve seen firsthand how complexity at scale reshapes the failure landscape and demands a different level of engineering intuition.
Co-designed or led multi-functional alignment on production methodologies adopted by other teams in an HVM environment.

Responsibilities

Partner with other HW engineering teams such as Silicon design and characterization teams, IO design and validation teams, system feature owners, Production Operations to determine coverage needs and constraints to resolve appropriate test conditions, diagnostic contents for production line screen.
Define requirements to SW and board teams to support and improve test infrastructure, debug knobs and data collection features needed to support manufacturing screens effectively.
Co-design testability scope and coverage enhancements for Nvidia's manufacturing testing with a focus on system-level test
Prototype and fine-tune speed, power, performance, yield, and quality on pre-production silicon.
Co-design , develop, and maintain system-level testing flows and incorporate takeaways from silicon and correlate to design.
Define procedures to facilitate correlation activities between production testing infrastructure and internal diagnostic programs
Support customer facing and quality teams during customer escalations to understand the issue and fix gaps identified in coverage.
Create key performance indicators used to evaluate the effectiveness of the new tests.
Initiate and drive process improvements and preventative actions through root cause analysis.