Develop and verify mixed-signal models for digital multiphase voltage regulators. Design SystemVerilog/Verilog testbenches, checkers, and verification flows for system-level control features. Model and simulate regulator behavior in steady-state, transient, fault, and configuration scenarios. Verify PWM modulation, phase management, current sensing, telemetry, protection, and control-loop interactions. Work collaboratively with analog, digital, firmware, validation, and system architecture teams. Debug model, RTL, firmware, and mixed-signal behavior, contributing to system-level verification enhancements.
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Job Type
Full-time
Career Level
Senior