Senior Staff Integration Design Engineer

Lattice Semiconductor•San Jose, CA

4d•$220,800•Onsite

About The Position

Lattice Semiconductor is looking for a Senior Staff Integration Design Engineer for our San Jose Office. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Requirements

BS or MS in Electronics/Computer/Electrical Engineering.
15+ years of experience in ASIC, SoC, or FPGA design and product-development.
Proven in-depth experience in Custom and Digital Design Implementation for IP/sector integration.
Expertise in Verilog and System Verilog is a must.
Expertise on the following: Digital Design Flow, RTL coding and verification, Lint check, elaboration/compilation, synthesis, equivalence check, SDC, and DFT flow and ATPG generation.
Expertise on the following: Custom Design Flow, Semiconductor principles and transistor-level analysis, Industry standard tools for schematic and layout entry (Cadence Virtuoso), Characterization, performance, and power simulations (SPICE preferred).
Expertise in coding/scripting (Perl, TCL, Shell, Skill, Python).
Familiarity with issue tracking and release workflows (e.g., JIRA) in a hardware engineering environment.
Working knowledge of SPICE-class circuit simulation, CMOS low-power design concepts (leakage, dynamic power, corner analysis), and correlating simulation results to silicon/bench measurement data.
Strong written and verbal communication skills; able to work across design, test, DFT, verification, and product engineering teams.

Nice To Haves

Experience in FPGA/CPLD design and integration is a plus.
Experience in IP and full-chip functional verification is a plus.
Experience in project leadership and product development cycle (planning, resourcing, tapeout, silicon characterization/validation) is a plus.
Experience with multiple process nodes/foundries (e.g., TSMC, Samsung) is a plus.

Responsibilities

Integrate IP blocks — including DDR PHY — into shared HPIO sectors to build sector- and full-chip-level views for FPGA platforms, utilizing both digital (synthesis, STA, DFT) and custom (physical/custom cell) design flows. This extends to the delivery of all corresponding models, views, and collaterals to different functional teams and the completion of all required checks and simulations for sign-off.
Own creation and maintenance of sector-level design constraints (SDC), including flat SDC generation for STA that reconciles clock frequency and constraint conflicts across multiple IP sources.
Run and maintain the digital implementation flow for the sector: RTL updates, synthesis (white-box/black-box), logical equivalence checking (LEC), static timing analysis (STA), and DFT scan integration (OPCG, scan port relocation, gating cells), coordinating with DFT and third-party IP teams.
Support custom/physical design integration tasks for the sector, including custom cell design and reuse across sectors, parasitic (SPEF) extraction with dummy fill for STA sign-off, and clock-critical signal routing/shielding review ahead of tapeout.
Track and resolve sector-level design issues through the engineering issue tracker (JIRA), maintain sector release notes and schedules, and publish regular status updates to cross-functional stakeholders (Design, DFT, Verification, Product Engineering).
Run full design verification (DV) regressions and sign-off checks for each sector release, and manage version-controlled releases of sector netlists, SDC, and related collateral.
Collaborate with IP Design, Product Engineering, and Test teams to integrate IP-level power data into full-chip power models, and to generate and validate current/power assumptions per supply domain to support board- and system-level power budgeting.
Review and cross check IP design's SPICE-level circuit simulation and PnR power results to characterize static and dynamic power across process, voltage, and temperature corners, and assess the power impact of any design changes.
Correlate simulated power models against silicon bench and production test data; support production test screen definition (e.g., leakage and worst-case process/voltage/temperature step screening) and resolve power data discrepancies tracked through the engineering issue tracker.