Senior Staff Engineer, Physical Design

Samsung Electronics•Austin, TX

1d•$180,200 - $270,400•Onsite

About The Position

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! As a Senior Staff GPU Physical Design Engineer, you will help shape the physical implementation and methodology innovation for high-performance GPU and system-level IP, enabling market-differentiating power, performance, and area (PPA) goals across Samsung’s advanced technology nodes. Your work will impact implementation quality, silicon readiness, and scalable execution for next-generation GPU IPs. In this senior individual contributor role, you will contribute to key stages of the physical design flow, from synthesis through floorplanning, timing closure, and signoff, while help advancing implementation strategies, methodology innovation, and scalable execution across parallel development cycles. You will collaborate closely with hardware, advanced design technology, and system-level teams to resolve complex implementation challenges and deliver robust, high-quality silicon for advanced-node designs. Leveraging your expertise in one or more technical areas, you help shape full-chip and block-level implementation, including floorplanning, placement, routing, timing closure, and signoff for complex GPU and SoC designs. You contribute to implementation strategies to achieve market-differentiating PPA targets, including power optimization, congestion management, STA-driven convergence, and reliability considerations across advanced-node designs. You help advancing methodology and flow innovation, including automation, tool optimization, and scalable design practices to improve implementation quality, productivity, and repeatability across projects. You enable cross-functional collaboration with architecture, RTL, advanced design technology, software, system-level teams, and external vendors, to adapt physical design flows for cutting-edge nodes and accelerate resolution of complex implementation and tool challenges. You inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation, and promoting continuous learning by staying ahead of physical design innovation for emerging GPU technologies.

Requirements

11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
7+ years of hands-on experience with full physical design implementation flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff.
Strong expertise in physical design implementation for complex GPU or SoC designs, including low-power design, physical verification (DRC/LVS), and advanced-node challenges
Strong experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerations
Strong proficiency with industry-standard EDA tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC)
Strong scripting and automation skills in Python, Tcl, Shell, or Perl
Strong analytical, debugging, and problem-solving skills with a data-driven approach for complex flow and design challenges
Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers.
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.

Nice To Haves

Experience with advanced-node designs (≤5nm) and high-performance GPU or SoC programs
Experience with DTCO methodologies and implementation scalability challenges

Responsibilities

Help shape full-chip and block-level implementation, including floorplanning, placement, routing, timing closure, and signoff for complex GPU and SoC designs.
Contribute to implementation strategies to achieve market-differentiating PPA targets, including power optimization, congestion management, STA-driven convergence, and reliability considerations across advanced-node designs.
Advance methodology and flow innovation, including automation, tool optimization, and scalable design practices to improve implementation quality, productivity, and repeatability across projects.
Enable cross-functional collaboration with architecture, RTL, advanced design technology, software, system-level teams, and external vendors, to adapt physical design flows for cutting-edge nodes and accelerate resolution of complex implementation and tool challenges.
Inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation, and promoting continuous learning by staying ahead of physical design innovation for emerging GPU technologies.