Senior Physical Design Engineer

MicrosoftHillsboro, OR

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s “Intelligent Cloud” mission by delivering the core infrastructure and foundational technologies for Microsoft's online businesses. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages Microsoft's computer chips, such as the Azure Cobalt. As Microsoft's cloud business grows, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality, and at the lowest cost is crucial. The CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving planning processes, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. This role is a key position within silicon design, supporting the team's mission.

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
  • Ability to meet Microsoft, customer and/or government security screening requirements.
  • Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • Must provide either proof of country of citizenship or proof of US residency or other protected status for assessment of eligibility to access export-controlled information.
  • Citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

  • BS/MS in Electrical or Computer Engineering or any related degree
  • Min 7+ years of experience in semiconductor design.
  • Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
  • Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
  • Production silicon tape-outs experience in advanced foundry process nodes.
  • Experience in low power design methodology for SOC
  • Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
  • Familiarity with various clock construction strategies for high speed designs
  • Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
  • Own complete PD execution of medium to large-size SOC block.
  • Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required.
  • Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues
  • Problem-solving and data analysis skills
  • Ability to communicate effectively with cross-functional teams

Responsibilities

  • Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
  • Responsible for clock construction and CTS.
  • Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology.
  • Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.
  • Responsible for RTL to GDS implementation in Physical Design domain.
  • Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
  • Foster collaboration across teams to deliver the possible solutions, aligned with a One Microsoft mindset.
  • Demonstrate technical expertise across various domains of Physical Design.
  • Clear communications on project status & planning.
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Benefits

  • Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances.
  • If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service