Senior Staff Engineer, Digital Verification and Methodology

Infineon•Lexington, KY
•$121,840 - $182,760•Onsite

About The Position

Join the thinkers, builders, and problem solvers behind tomorrow’s technology. As a Senior Staff Engineer, Digital Verification and Methodology on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Join a collaborative team that values diverse perspectives and leads functional verification for advanced integrated circuits while scaling reusable methodologies across global development sites.

Requirements

  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field
  • 5+ years in ASIC, SoC, or FPGA functional verification with ownership of complex block, subsystem, or chip-level deliverables
  • Expert proficiency in SystemVerilog, UVM, object-oriented testbench architecture, constrained-random verification, functional coverage, and assertion-based verification
  • Ability to translate specifications and microarchitecture into verification plans, environments, tests, checkers, coverage models, and sign-off evidence
  • Written and spoken English at C1 level

Nice To Haves

  • Strong debugging skills with a major simulation and debug toolchain
  • Proficiency in Linux development and scripting or programming with Python, Tcl, Bash, C, or C++ for automation
  • Experience with RTL design and digital architecture
  • Exposure to Ethernet or complex protocols
  • Security verification for cryptographic accelerators or secure subsystems
  • Power-aware verification using UPF
  • Practical use of AI or machine learning and AI-enabled EDA tools

Responsibilities

  • Lead end-to-end verification strategy from requirements analysis through sign-off
  • Architect reusable SystemVerilog UVM environments and scalable object-oriented testbenches
  • Implement constrained-random and assertion-based verification with robust functional coverage
  • Drive metric-driven coverage closure and establish clear quality criteria
  • Translate specifications and microarchitecture into tests, checkers, coverage models, and sign-off evidence
  • Improve verification methodologies, automation, and tool flows across projects and development sites
  • Collaborate with design, firmware, and system teams to debug issues and ensure reliable hardware-software interaction

Benefits

  • Incentive plan
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