Senior Staff Digital Verification Engineer

Renesas Electronics•Duluth, GA

3d•Onsite

About The Position

Renesas is seeking a talented Senior Staff Digital Verification Engineer for their memory interface products, which are crucial for datacenters supporting AI and cloud computing. This role involves the development of digital sections for leading-edge memory data buffer chips, specifically for DDR5, DDR6, and future technologies. The engineer will be responsible for the verification of DDR6 Data Buffer to ensure it meets functional and performance specifications, integrating and testing at both system and block levels using UVM methodology.

Requirements

Masters in Electrical Engineering, Computer Engineering, or equivalent with 7+ years of experience.
Bachelor's Degree in Electrical Engineering, Computer Engineering, or equivalent with 9+ years of experience.

Responsibilities

Verification of DDR6 Data Buffer to meet functional and performance specifications.
Integrate and test on System-level and block level using UVM methodology.
Develop verification plan based on specifications.
Support in Verification planning, maintenance, feature extraction, verification tests, coverage and checker development.
Develop efficient, reusable state-of-the-art verification environments and testbench structures.
Optimize solutions for key indicators such as reusability, performance and ease of use.
Identify and communicate improvements that may ease verification and/or improve design behavior.
Support in optimizing UVM based testbench.
Take ownership of verification environments for assigned blocks, and tools appointed to you as Expert User.
Participate in feasibility studies.
Drive the Memory interface products verification effort, including defining the verification strategy, developing test plans, coverage, and executing tests.
Drive and quality control the creation of a verification test plan.
Work closely with the design team to ensure that the design meets the requirements and is testable.
Identify and drive improvements to the verification process to ensure the highest levels of quality and efficiency.
Drive and monitor coverage of design verification.
Provide regular updates to management on the status of the verification effort.